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參數(shù)資料
| 型號： | CY62136EV30LL-45ZSXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2-Mbit (128K x 16) Static RAM |
| 中文描述： | 128K X 16 STANDARD SRAM, 45 ns, PDSO44 |
| 封裝： | LEAD FREE, TSOP2-44 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 567K |
| 代理商： | CY62136EV30LL-45ZSXI |
CY62136EV30
MoBL
Document #: 38-05569 Rev. *B
Page 5 of 12
Switching Characteristics
Over the Operating Range
[10, 11, 12, 13]
Parameter
Description
45 ns
Unit
Min.
Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[13]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
10.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
CC(typ)
/2, input
pulse levels of 0 to V
, and output loading of the specified I
/I
OH
as shown in the “AC Test Loads and Waveforms” section.
11. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
12.t
, t
, t
, and t
transitions are measured when the outputs enter a high impedence state.
13.The internal Write time of the memory is defined by the overlap of WE, CE
= V
, BHE and/or BLE = V
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z
[11]
OE HIGH to High Z
[11, 12]
CE LOW to Low Z
[11]
CE HIGH to High Z
[11, 12]
CE LOW to Power-Up
CE HIGH to Power-Down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[11]
BLE/BHE HIGH to HIGH Z
[11, 12]
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
10
45
22
5
18
10
18
0
45
22
5
18
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High-Z
[11, 12]
WE HIGH to Low-Z
[11]
45
35
35
0
0
35
35
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
18
10
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62136FV30 | 2-Mbit (128K x 16) Static RAM |
| CY62136FV30LL | 2-Mbit (128K x 16) Static RAM |
| CY62136FV30LL-45BVXI | 2-Mbit (128K x 16) Static RAM |
| CY62136FV30LL-45ZSXI | 2-Mbit (128K x 16) Static RAM |
| CY62136FV30LL-55ZSXE | 2-Mbit (128K x 16) Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62136EV30LL-45ZSXI | 制造商:Cypress Semiconductor 功能描述:IC SRAM 2MBIT PARALLEL 45NS TSOP-44 制造商:Cypress Semiconductor 功能描述:IC, SRAM, 2MBIT, PARALLEL, 45NS, TSOP-44 |
| CY62136EV30LL-45ZSXIT | 功能描述:靜態(tài)隨機存取存儲器 SLO 3.0V SUPER LO PWR 128KX16 靜態(tài)隨機存取存儲器 IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62136FV30 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (128 K x 16) Static RAM Automatic power down when deselected |
| CY62136FV30_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2 Mbit (128K x 16) Static RAM |
| CY62136FV30_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (128 K x 16) Static RAM Automatic power down when deselected |
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