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參數(shù)資料
| 型號： | CY62136CV18LL-70BVI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 128K x 16 Static RAM |
| 中文描述： | 128K X 16 STANDARD SRAM, 70 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, VFBGA-48 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 173K |
| 代理商： | CY62136CV18LL-70BVI |
2-Mbit (128K x 16) Static RAM
CY62136V MoBL
Cypress Semiconductor Corporation
Document #: 38-05087 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised September 24, 2004
Features
Temperature Ranges
— Commercial : 0°C to 70°C
— Industrial :
40°C to 85°C
— Automotive :
40°C to 125°C
High speed: 55 ns and 70 ns
70-ns speed bin offered in both Industrial and
Automotive grades
Wide voltage range: 2.7V-3.6V
Ultra-low active, standby power
Easy memory expansion with CE and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
Package available in a standard 44-pin TSOP Type II
(forward pinout) package
Functional Description
[1]
The CY62136V is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life
(MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE HIGH). The input/output pins (I/O
0
through
I/O
15
) are placed in a high-impedance state when: deselected
(CE HIGH), outputs are disabled (OE HIGH), BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
16
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the Truth Table at the back of this data sheet for a complete
description of read and write modes.
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
128K x 16
RAM Array
2048 x 1024
I/O
0
– I/O
7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
BLE
I/O
8
– I/O
15
CE
WE
BHE
A
1
A
0
A
9
A
10
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY62136CV30 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2M (128K x 16) Static RAM |
| CY62136CV30_06 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (128K x 16) Static RAM |
| CY62136CV30LL-55BAI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2M (128K x 16) Static RAM |
| CY62136CV30LL-55BVI | 制造商:Cypress Semiconductor 功能描述: |
| CY62136CV30LL-70BAI | 制造商:Cypress Semiconductor 功能描述: |
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