參數(shù)資料
型號(hào)： CY62128VLL-70ZAC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： 128K x 8 Static RAM
中文描述： 128K X 8 STANDARD SRAM, 70 ns, PDSO32
封裝： 8 X 13.40 MM, STSOP1-32
文件頁(yè)數(shù)： 1/12頁(yè)
文件大?。?/td> 178K
代理商： CY62128VLL-70ZAC
128K x 8 Static RAM
CY62128V Family
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
March 27, 2000
amily
Features
Low voltage range:
—2.7V–3.6V (CY62128V)
—2.3V–2.7V (CY62128V25)
—1.6V–2.0V (CY62128V18)
Low active power and standby power
Easy memory expansion with CE and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
Functional Description
The CY62128V family is composed of three high-performance
CMOS static RAMs organized as 131,072 words by 8 bits.
Easy memory expansion is provided by an active LOW Chip
Enable (CE
1
), an active HIGH Chip Enable (CE
2
), an active
LOW Output Enable (OE) and three-state drivers. These de-
vices have an automatic power-down feature, reducing the
power consumption by over 99% when deselected. The
CY62128V family is available in the standard 450-mil-wide
SOIC, 32-lead TSOP-I, and STSOP packages.
Writing to the device is accomplished by taking Chip Enable
one (CE
1
) and Write Enable (WE) inputs LOW and the Chip
Enable two (CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is then written into the location specified on the
address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip En-
able one (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable two (CE
2
) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
1
A
1
A
Logic Block Diagram
Pin Configurations
Top View
SOIC
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
2
I/O
1
I/O
2
I/O
3
51ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
A
1
CE
1
A
1
A
9
62128V-1
62128V-2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
19
18
20
24
23
22
21
25
28
27
26
29
32
31
30
16
17
GND
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
WE
A
13
A
8
A
9
A
11
V
CC
A
15
CE
2
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
NC
I/O
0
I/O
1
I/O
2
CE
1
OE
A
10
A
6
A
5
A
7
A
16
A
14
A
12
WE
CE
2
A
15
V
NC
A
4
A
13
A
8
A
9
OE
A
10
TSOP I / STSOP
Top View
(not to scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
I/O
1
I/O
0
A
0
I/O
I/O
7
I/O
6
I/O
4
I/O
3
I/O
5
CE
1
A
11
17
A
1
A
2
A
3
A
6
A
7
A
12
A
16
NC
A
14
WE
A
13
A
8
A
9
A
11
V
CC
A
15
A
4
A
5
OE
TSOP I
1
6
5
2
3
4
7
32
27
28
31
30
29
26
21
22
25
24
23
19
20
I/O
2
GND
I/O
3
I/O
1
I/O
7
CE
1
A
10
I/O
4
I/O
5
I/O
6
I/O
0
17
18
8
9
10
11
12
13
14
15
16
CE
2
A
1
A
0
A
3
A
2
(not to scale)
ReTop View
62128V-3
62128V-4
相關(guān)PDF資料
PDF描述
CY62128V18LL-200SC 128K x 8 Static RAM
CY62128V18LL-200SI 128K x 8 Static RAM
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CY62128V18L-200ZAC 128K x 8 Static RAM
CY62128V18L-200ZAI 128K x 8 Static RAM
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