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參數(shù)資料
| 型號(hào)： | CY62128EV30LL-45SXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 1 Mbit (128K x 8) Static RAM |
| 中文描述： | 128K X 8 STANDARD SRAM, 45 ns, PDSO32 |
| 封裝： | 0.450 INCH, LEAD FREE, SOIC-32 |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 861K |
| 代理商： | CY62128EV30LL-45SXI |
Document #: 38-05579 Rev. *C
Page 5 of 11
CY62128EV30 MoBL
Switching Characteristics
(Over the Operating Range)
[10, 11]
Parameter
Description
45 ns (Ind’l/Auto-A)
55 ns (Auto-E)
Unit
Min
Max
Min
Max
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
Read Cycle Time
45
55
ns
Address to Data Valid
45
55
ns
Data Hold from Address Change
10
10
ns
CE LOW to Data Valid
45
55
ns
OE LOW to Data Valid
OE LOW to Low Z
[12]
OE HIGH to High Z
[12,13]
CE LOW to Low Z
[12]
CE HIGH to High Z
[12, 13]
22
25
ns
5
5
ns
18
20
ns
t
LZCE
t
HZCE
10
10
ns
18
20
ns
t
PU
t
PD
Write Cycle
[14]
CE LOW to Power Up
0
0
ns
CE HIGH to Power Up
45
55
ns
t
WC
t
SCE
t
AW
t
HA
t
SA
Write Cycle Time
45
55
ns
CE LOW to Write End
35
40
ns
Address Setup to Write End
35
40
ns
Address Hold from Write End
0
0
ns
Address Setup to Write Start
0
0
ns
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
WE Pulse Width
35
40
ns
Data Setup to Write End
25
25
ns
Data Hold from Write End
WE LOW to High Z
[12, 13]
WE HIGH to Low Z
[12]
0
0
ns
18
20
ns
10
10
ns
Notes:
11.Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
CC(typ)
/2, input
pulse levels of 0 to V
, and output loading of the specified I
/I
OH
as shown in the
“AC Test Loads and Waveforms” on page 4
.
12.At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
HZWE
is less than t
LZWE
for any given device.
13.t
, t
, and t
transitions are measured when the output enter a high impedance state.
14.The internal write time of the memory is defined by the overlap of WE, CE = V
. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62128EV30LL-45SXI_ | 制造商:Cypress Semiconductor 功能描述: |
| CY62128EV30LL-45SXIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1M MOBL ULTRA LO PWR HI SPD IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62128EV30LL-45SXIT_ | 制造商:Cypress Semiconductor 功能描述: |
| CY62128EV30LL-45ZAXA | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1-Mbit Static RAM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62128EV30LL-45ZAXAT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1-Mbit Static RAM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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