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參數(shù)資料
| 型號： | CY62128E |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1-Mbit (128K x 8) Static RAM |
| 中文描述： | 1兆位（128K的× 8）靜態(tài)RAM |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 862K |
| 代理商： | CY62128E |
Document #: 38-05485 Rev. *E
Page 5 of 11
CY62128E MoBL
Switching Characteristics
(Over the Operating Range)
[12]
Parameter
Description
45 ns (Ind’l/Auto-A)
55 ns (Auto-E)
Unit
Min
Max
Min
Max
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[15]
Read Cycle Time
45
55
ns
Address to Data Valid
45
55
ns
Data Hold from Address Change
10
10
ns
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[13]
OE HIGH to High-Z
[13, 14]
CE
1
LOW and CE
2
HIGH to Low-Z
[13]
CE
1
HIGH or CE
2
LOW to High-Z
[13, 14]
CE
1
LOW and CE
2
HIGH to Power Up
CE
1
HIGH or CE
2
LOW to Power Down
45
55
ns
22
25
ns
5
5
ns
18
20
ns
10
10
ns
18
20
ns
0
0
ns
45
55
ns
t
WC
t
SCE
t
AW
Write Cycle Time
45
55
ns
CE
1
LOW and CE
2
HIGH to Write End
Address Setup to Write End
35
40
ns
35
40
ns
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Address Hold from Write End
0
0
ns
Address Setup to Write Start
0
0
ns
WE Pulse Width
35
40
ns
Data Setup to Write End
25
25
ns
Data Hold from Write End
WE LOW to High-Z
[13, 14]
WE HIGH to Low-Z
[13]
0
0
ns
18
20
ns
10
10
ns
Notes
12.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns (1V/ns) or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3V, and output loading of the specified I
OL
/I
as shown in the
“AC Test Loads and Waveforms” on page 4
.
13.At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
HZWE
is less than t
LZWE
for any given device.
14.t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
15.The internal Write time of the memory is defined by the overlap of WE, CE
= V
. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62128E_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1-Mbit (128K x 8) Static RAM |
| CY62128E_13 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1-Mbit (128 K x 8) Static RAM |
| CY62128ELL | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1-Mbit (128K x 8) Static RAM |
| CY62128ELL-45SXA | 功能描述:靜態(tài)隨機存取存儲器 1M MOBL ULTRA Lo PWR HI SPD ASYNC 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62128ELL-45SXAKJ | 制造商:Cypress Semiconductor 功能描述: |
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