參數(shù)資料
型號： CY62128DV30
廠商： Cypress Semiconductor Corp.
英文描述： 1 Mb (128K x 8) Static RAM
中文描述： 1字節(jié)（128K的× 8）靜態(tài)RAM
文件頁數(shù)： 6/11頁
文件大?。?/td> 196K
代理商： CY62128DV30
CY62128DV30
MoBL
Document #: 38-05231 Rev. *C
Page 6 of 11
Read Cycle No. 2 (OE Controlled)
[10, 13, 14]
Write Cycle No. 1 (WE Controlled)
[11,
15, 16, 17]
Notes:
14. Address valid prior to or coincident with CE
1
transition LOW and CE
2
transition HIGH.
15. Data I/O is high-impedance if OE = V
.
16. If CE
goes HIGH or CE
goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Switching Waveforms
(continued)
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
1
I
CC
I
SB
IMPEDANCE
ADDRESS
CE
2
DATA OUT
V
SUPPLY
CURRENT
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
1
ADDRESS
CE
2
WE
DATA I/O
相關PDF資料
PDF描述
CY62128DV30L-55SI 1 Mb (128K x 8) Static RAM
CY62128DV30L-55ZAI 1 Mb (128K x 8) Static RAM
CY62128DV30L-55ZI 1 Mb (128K x 8) Static RAM
CY62128DV30L-55ZRI 1 Mb (128K x 8) Static RAM
CY62128DV30L-70SI 1 Mb (128K x 8) Static RAM
相關代理商/技術(shù)參數(shù)
參數(shù)描述
CY62128DV30_06 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1-Mb (128K x 8) Static RAM
CY62128DV30L-55SI 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 2.5V/3.3V 1M-Bit 128K x 8 55ns 32-Pin SOIC 制造商:Rochester Electronics LLC 功能描述:1MB (128K X 8)- 3.0V SLOW ASYNCH SRAM - Bulk
CY62128DV30L-55SIT 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 2.5V/3.3V 1M-Bit 128K x 8 55ns 32-Pin SOIC T/R
CY62128DV30L-55ZAI 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:1MB (128K X 8)- 3.0V SLOW ASYNCH SRAM - Bulk
CY62128DV30L-55ZAIT 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 2.5V/3.3V 1M-Bit 128K x 8 55ns 32-Pin STSOP-I T/R 制造商:Rochester Electronics LLC 功能描述:1MB (128K X 8)- 3.0V SLOW ASYNCH SRAM - Tape and Reel
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