參數(shù)資料
型號(hào)： CY62128BLL-70ZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： Dual-Bit Dual Supply Transceiver with Configurable Voltage Translation and 3-State Outputs 8-US8 -40 to 85
中文描述： 128K X 8 STANDARD SRAM, 70 ns, PDSO32
封裝： 8 X 20 MM, TSOP1-32
文件頁數(shù)： 1/11頁
文件大小： 340K
代理商： CY62128BLL-70ZC
128K x 8 Static RAM
CY62128B
MoBL
Cypress Semiconductor Corporation
Document #: 38-05300 Rev. *C
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised February 14, 2005
Features
Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
4.5V – 5.5V operation
CMOS for optimum speed/power
Low active power
(70 ns, LL version, Commercial, Industrial)
— 82.5 mW (max.) (15 mA)
Low standby power
(70 ns, LL version, Commercial, Industrial)
— 110
μ
W (max.) (15
μ
A)
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
, and OE options
Functional Description
[1]
The CY62128B is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE
1
),
an active HIGH Chip Enable (CE
2
), an active LOW Output
Enable (OE), and three-state drivers. This device has an
automatic
power-down
feature
consumption by more than 75% when deselected.
Writing to the device is accomplished by taking Chip Enable
One (CE
1
) and Write Enable (WE) inputs LOW and Chip
Enable Two (CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is then written into the location specified on the
address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable One (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE
2
) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY62128B is available in a standard 450-mil-wide SOIC,
32-pin TSOP type I and STSOP packages.
that
reduces
power
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
1
A
1
A
Logic Block Diagram
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
I/O1
I/O2
I/O3
512x256x8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
A
A
1
A
A
CE2
A
1
A
9
相關(guān)PDF資料
PDF描述
CY62128BLL-70ZE Dual-Bit Dual Supply Transceiver with Configurable Voltage Translation and 3-State Outputs 8-US8 -40 to 85
CY62128BLL-70ZXE 128K x 8 Static RAM
CY62128BLL-70ZRXE Circular Connector; MIL SPEC:MIL-C-26482, Series I, Crimp; Body Material:Aluminum; Series:PT01; No. of Contacts:19; Connector Shell Size:14; Connecting Termination:Crimp; Circular Shell Style:Cable Receptacle; Body Style:Straight
CY62128BLL-70ZAE 128K x 8 Static RAM
CY62128BLL-70ZXI Coaxial Cable; Impedance:75ohm; Conductor Size AWG:30; No. Strands x Strand Size:7 x 38; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:Yes
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY62128BLL-70ZE 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:128K x 8 Static RAM
CY62128BLL-70ZI 制造商:Rochester Electronics LLC 功能描述:
CY62128BLL-70ZRC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM
CY62128BLL-70ZRI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM
CY62128BLL-70ZRXE 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 SLO 5.0V SUPER LO PWR 128K X 8 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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