參數(shù)資料
型號(hào): CY62128-55SC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): DRAM
英文描述: 128K x 8 Static RAM
中文描述: 128K X 8 STANDARD SRAM, 55 ns, PDSO32
封裝: 0.450 INCH, PLASTIC, SOIC-32
文件頁(yè)數(shù): 4/11頁(yè)
文件大?。?/td> 196K
代理商: CY62128-55SC
CY62128DV30
MoBL
Document #: 38-05231 Rev. *C
Page 4 of 11
AC Test Loads and Waveforms
Data Retention Characteristics
Data Retention Waveform
Note:
7.
Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100 us.
Thermal Resistance
Parameter
θ
JA
θ
JC
Description
Test Conditions
SOIC TSOP I STSOP Unit
69
93
34
17
Thermal Resistance (Junction to Ambient)
[6]
Still Air, soldered on a 3 x 4.5 inch,
Thermal Resistance (Junction to Case)
[6]
two-layer printed circuit board
65
15
°C/W
°C/W
V
CC
Typ
V
CC
OUTPUT
R2
C = 50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
TH
Equivalent to:
TH
éVENIN EQUIVALENT
R
TH
ALL INPUT PULSES
R1
Rise Time:
1 V/ns
Fall Time:
1 V/ns
Parameters
R1
R2
R
TH
V
TH
3.0V (2.7
3.6V)
1103
1554
645
1.75
Unit
V
2.5V (2.2
2.7V)
16600
15400
8000
1.2
Parameter
V
DR
I
CCDR
Description
Conditions
Min.
1.5
Typ.
[5]
Max. Unit
V
CC
for Data Retention
Data Retention Current
V
μ
A
V
CC
= 1.5V, CE
1
> V
CC
0.2V, CE
2
< 0.2V,
V
IN
> V
CC
0.2V or V
IN
< 0.2V
L
LL
4
3
t
CDR[5]
t
R[7]
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
μ
s
100
V
CC(min.)
t
R
V
CC(min.)
t
CDR
V
DR
> 1.5V
DATA RETENTION MODE
CE
1
or
V
CC
CE
2
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