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參數(shù)資料
| 型號： | CY62127V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64K x 16 Static RAM(64K x 16 靜態(tài)RAM) |
| 中文描述： | 64K的× 16靜態(tài)RAM（64K的× 16靜態(tài)RAM）的 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 192K |
| 代理商： | CY62127V |
64K x 16 Static RAM
CY62127V
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
June 2, 1999
Features
2.7V–3.6V operation
CMOS for optimum speed/power
Low active power (70 ns)
—198 mW (max.) (55 mA)
Low standby power (70 ns, LL version)
—54
μ
W (max.) (15
μ
A)
Automatic power-down when deselected
—
Power down either with CE or BHE and BLE HIGH
Independent control of Upper and Lower Bytes
Available in 44-pin TSOP II (forward)
Functional Description
The CY62127V is a high-performance CMOS Static RAM or-
ganized as 65,536 words by 16 bits. This device has an auto-
matic power-down feature that significantly reduces power
consumption by 99% when deselected. The device enters
power-down mode when CE is HIGH or when CE is LOW and
both BLE and BHE are HIGH.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
1
through I/O
8
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
9
through I/O
16
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
1
to I/O
8
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
9
to I/O
16
. See
the truth table at the back of this datasheet for a complete
description of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY62127V is available in standard 44-pin TSOP Type II
(forward pinout) and mini-BGA packages.
Logic Block Diagram
Pin Configurations
TSOP II (Forward)
64K x 16
RAM Array
1024 X 1024
I/O
1
–I/O
8
R
A
10
A
9
A
7
A
6
A
3
A
2
A
1
A
0
COLUMN DECODER
A
5
A
8
A
1
A
1
A
1
S
DATA IN DRIVERS
BLE
I/O
9
–I/O
16
OE
WE
A
4
A
11
A
12
62127V–1
62127V–2
WE
A
15
A
14
A
13
A
12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
Top View
41
44
43
42
16
17
29
28
V
CC
V
SS
I/O
5
I/O
6
A
4
A
3
A
2
A
1
A
0
OE
BHE
BLE
V
SS
V
CC
I/O
12
I/O
11
I/O
10
I/O
9
A
5
A
6
A
7
I/O
16
I/O
15
I/O
14
I/O
13
CE
I/O
1
I/O
2
I/O
3
I/O
4
NC
A
8
A
9
A
10
A
11
18
19
20
21
27
26
25
24
22
23
NC
I/O
7
I/O
8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62128BLL-70ZI | Dual-Bit Dual Supply Transceiver with Configurable Voltage Translation and 3-State Outputs 8-US8 -40 to 85 |
| CY62128BLL-55ZRI | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT02; No. of Contacts:6; Connector Shell Size:10; Connecting Termination:Solder; Circular Shell Style:Box Mount Receptacle |
| CY62128BLL-70ZAXE | 128K x 8 Static RAM |
| CY62128BLL-55ZAXI | 128K x 8 Static RAM |
| CY62128BLL-70ZAXI | 128K x 8 Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62127V-55BAC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
| CY62127V-55ZC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
| CY62127V-70BAC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
| CY62127V-70ZC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
| CY62127VL-55BAC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
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