參數(shù)資料
型號(hào): CY62126BVLL-70BAI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 64K x 16 Static RAM
中文描述: 64K X 16 STANDARD SRAM, 70 ns, PBGA48
封裝: 7 X 7 MM, FBGA-48
文件頁(yè)數(shù): 6/11頁(yè)
文件大?。?/td> 398K
代理商: CY62126BVLL-70BAI
CY62126DV30
MoBL
Document #: 38-05230 Rev. *E
Page 6 of 11
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[14, 15]
Read Cycle No. 2 (OE Controlled)
[15, 16]
Notes:
14.Device is continuously selected. OE, CE = V
IL
, BHE, BLE = V
IL
.
15.WE is HIGH for Read cycle.
16.Address valid prior to or coincident with CE, BHE, BLE transition LOW.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
I
CC
I
SB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
CC
SUPPLY
CURRENT
t
HZBE
BHE/BLE
t
t
LZOE
ADDRESS
t
DOE
t
DBE
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