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參數(shù)資料
| 型號： | CY3930Z208-233MBC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | CPLDs at FPGA Densities |
| 中文描述： | CPLD器件在FPGA的密度 |
| 文件頁數(shù)： | 19/86頁 |
| 文件大?。?/td> | 1235K |
| 代理商： | CY3930Z208-233MBC |
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Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 19 of 86
Cluster Memory Timing Parameter Descriptions
Over the Operating Range
t
CKIN
t
IOREGPIN
PLL Parameters
t
MCCJ
t
DWSA
t
DWOSA
t
LOCK
t
INDUTY
f
PLLI
f
PLLO
f
PLLVCO
P
SAPLLI
f
MPLLI
Delay from the clock pin to the input of the clock driver
Delay from the I/O pin to the input of the I/O register
Maximum cycle to cycle jitter time
PLL zero phase delay with clock tree deskewed
PLL zero phase delay without clock tree deskewed
Lock time for the PLL
Input duty cycle
Input frequency of the PLL
Output frequency of the PLL
PLL VCO frequency of operation
Percentage modulation allowed (spread awareness) on the PLL input clock
Frequency of modulation allowed on PLL input clock. This specifies how fast the f
PLLI
sweeps between f
PLLI
*
(1–P
SAPLLI
/100) and f
PLLI
* (1+ P
SAPLLI
/100)
JTAG Parameters
t
JCKH
TCLK HIGH time
t
JCKL
TCLK LOW time
t
JCP
TCLK clock period
t
JSU
JTAG port set-up time (TDI/TMS inputs)
t
JH
JTAG port hold time (TDI/TMS inputs)
t
JCO
JTAG port clock to output time (TDO)
t
JXZ
JTAG port valid output to high impedance (TDO)
t
JZX
JTAG port high impedance to valid output (TDO)
Switching Characteristics — Parameter Descriptions
Over the Operating Range
[13]
(continued)
Parameter
Description
Parameter
Asynchronous Mode Parameters
t
CLMAA
t
CLMPWE
t
CLMSA
t
CLMHA
t
CLMSD
t
CLMHD
Synchronous Mode Parameters
t
CLMCYC1
Description
Cluster memory access time. Delay from address change to Read data out
Write Enable pulse width
Address set-up to the beginning of Write Enable with both signals from the same I/O block
Address hold after the end of Write Enable with both signals from the same I/O block
Data set-up to the end of Write Enable
Data hold after the end of Write Enable
Clock cycle time for flow through Read and Write operations (from macrocell register through cluster memory
back to a macrocell register in the same cluster)
Clock cycle time for pipelined Read and Write operations (from cluster memory input register through the
memory to cluster memory output register)
Address, data, and WE set-up time of pin inputs, relative to a global clock
Address, data, and WE hold time of pin inputs, relative to a global clock
Global clock to data valid on output pins for flow through data
Global clock to data valid on output pins for pipelined data
Cluster memory input clock to macrocell clock in the same cluster
Cluster memory output clock to macrocell clock in the same cluster
Macrocell clock to cluster memory input clock in the same cluster
t
CLMCYC2
t
CLMS
t
CLMH
t
CLMDV1
t
CLMDV2
t
CLMMACS1
t
CLMMACS2
t
MACCLMS1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY3930Z208-233MBI | CPLDs at FPGA Densities |
| CY3930Z208-233NC | CPLDs at FPGA Densities |
| CY3930Z208-233NI | CPLDs at FPGA Densities |
| CY3930Z208-233NTI | CPLDs at FPGA Densities |
| CY3930Z208-83BBC | CPLDs at FPGA Densities |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY3930Z208-233MGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY3930Z208-233MGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY3930Z208-233NTC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY3930Z208-83NC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY3930Z256-125MBC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
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