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參數(shù)資料
| 型號： | CY3930V484-233BBC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | CPLDs at FPGA Densities |
| 中文描述： | CPLD器件在FPGA的密度 |
| 文件頁數(shù)： | 5/86頁 |
| 文件大?。?/td> | 1235K |
| 代理商： | CY3930V484-233BBC |
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Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 5 of 86
Logic Block
The LB is the basic building block of the Delta39K architecture.
It consists of a product term array, an intelligent product-term
allocator, and 16 macrocells.
Product Term Array
Each logic block features a 72 x 83 programmable product
term array. This array accepts 36 inputs from the PIM. These
inputs originate from device pins and macrocell feedbacks as
well as cluster memory and channel memory feedbacks.
Active LOW and active HIGH versions of each of these inputs
are generated to create the full 72-input field. The 83 product
terms in the array can be created from any of the 72 inputs.
Of the 83 product terms, 80 are for general-purpose use for
the 16 macrocells in the logic block. Two of the remaining three
product terms in the logic block are used as asynchronous set
and asynchronous reset product terms. The final product term
is the Product Term clock (PTCLK) and is shared by all 16
macrocells within a logic block.
Product Term Allocator
Through the product term allocator,
Warp
software automati-
cally distributes the 80 product terms as needed among the 16
macrocells in the logic block. The product term allocator
provides two important capabilities without affecting perfor-
mance: product term steering and product term sharing.
Product Term Steering
Product term steering is the process of assigning product
terms to macrocells as needed. For example, if one macrocell
requires ten product terms while another needs just three, the
product term allocator will “steer” ten product terms to one
macrocell and three to the other. On Delta39K devices,
product terms are steered on an individual basis. Any number
between 1 and 16 product terms can be steered to any
macrocell.
Product Term Sharing
Product term sharing is the process of using the same product
term among multiple macrocells. For example, if more than
one function has one or more product terms in its equation that
are common to other functions, those product terms are only
programmed once. The Delta39K product term allocator
allows sharing across groups of four macrocells in a variable
fashion. The software automatically takes advantage of this
capability so that the user does not have to intervene.
Note that neither product term sharing nor product term
steering have any effect on the speed of the product. All
steering and sharing configurations have been incorporated in
the timing specifications for the Delta39K devices.
.
Logic
Block
0
Logic
Block
1
Logic
Block
3
Logic
Block
2
Cluster
Memory
0
PIM
Logic
Block
7
Logic
Block
6
Logic
Block
4
Logic
Block
5
Cluster
Memory
1
64 Inputs From
Horizontal Routing
Channel
64 Inputs From
Vertical Routing
Channel
144 Outputs to
Horizontal and Vertical
cluster-to-channel PIMs
Clock Inputs
GCLK[3:0]
C
C
C
C
C
C
CC = Carry Chain
16
36
16
36
16
36
16
36
16
36
16
36
16
36
8
25
8
25
4
16
36
Figure 3. Delta39K Logic Block Cluster Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY3930V484-233BBI | CPLDs at FPGA Densities |
| CY3930V484-233BGC | CPLDs at FPGA Densities |
| CY3930V484-233BGI | CPLDs at FPGA Densities |
| CY3930V484-233MBC | CPLDs at FPGA Densities |
| CY3930V484-233MBI | CPLDs at FPGA Densities |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY3930Z208-125BBC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY3930Z208-125BBI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY3930Z208-125BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY3930Z208-125BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY3930Z208-125MBC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
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