- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380137 > CY39200V256-233BBC (Cypress Semiconductor Corp.) CPLDs at FPGA Densities PDF資料下載
參數(shù)資料
| 型號(hào)： | CY39200V256-233BBC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | CPLDs at FPGA Densities |
| 中文描述： | CPLD器件在FPGA的密度 |
| 文件頁(yè)數(shù)： | 16/86頁(yè) |
| 文件大?。?/td> | 1235K |
| 代理商： | CY39200V256-233BBC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)當(dāng)前第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 16 of 86
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
(39K200, 208 EQFP) .................................–45
°
C to +125
°
C
Storage Temperature
(all other densities and packages)..............–65
°
C to +150
°
C
Soldering Temperature.................................................220
°
C
Ambient Temperature with
Power Applied...............................................–40
°
C to +85
°
C
Operating Range
Junction Temperature...................................................135°C
V
CC
to Ground Potential...................................–0.5V to 4.6V
V
CCIO
to Ground Potential................................–0.5V to 4.6V
DC Voltage Applied to Outputs
in High-Z state..................................................–0.5V to 4.5V
DC Input voltage...............................................–0.5V to 4.5V
DC Current into Outputs........................................± 20 mA
[6]
Static Discharge Voltage
(per JEDEC EIA./JESD22–A114A)............................>2001V
Latch-up Current .....................................................>200 mA
Note:
6.
7.
DC current into outputs is 36 mA with HSTL III, 48 mA with HSTL IV, and 36 mA with GTL+ (with 25W pull-up resistor and V
= 1.5).
Input Leakage current is ±10
μ
A for all the pins on all the Delta39K package except the following pins in Delta39K100 packages: The input leakage current spec
for these pins in ±200
μ
A
Delta39K100
Package
388-BGA
484-FBGA
676-FBGA
8.
Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V
= 0.5V has been chosen to avoid test
problems caused by tester-ground degradation. Tested initially and after any design or process changes that may affect these parameters.
Range
Commercial
Ambient
Temperature
0
°
C to +70
°
C
Junction
Temperature
0
°
C to +85
°
C
Output
Condition
3.3V
2.5V
1.8V
1.5V
3.3V
2.5V
1.8V
1.5V
V
CCIO
3.3V ± 0.3V
2.5V ± 0.2V
1.8V ± 0.15V
1.5V ± 0.1V
[5]
3.3V ± 0.3V
2.5V ± 0.2V
1.8V ± 0.15V
1.5V ± 0.1V
[5]
V
CC
V
CCJTAG
/
V
CCCNFG
Same as
V
CCIO
V
CCPLL
V
CCPRG
Same as
V
CC
3.3V ± 0.3V or
2.5V ± 0.2V
(39KV)
3.3V ±
0.3V
Industrial
–40
°
C to +85°C
–40
°
C to +100°C
DC Characteristics
Parameter
V
DRINT
Description
Test
Conditions
V
CCIO
= 3.3V V
CCIO
= 2.5V
Min.
Max.
1.5
V
CCIO
= 1.8V
Min.
1.5
Unit
V
Min.
1.5
Max.
Max.
Data Retention V
CC
Voltage
(config data may be lost below this)
Data Retention V
CCIO
Voltage
(config data may be lost below this)
Input Leakage Current
Output Leakage Current
V
DRIO
1.2
1.2
1.2
V
I
IX[7]
I
OZ
GND
≤
V
I
≤
3.6V
GND
≤
V
O
≤
V
CCIO
V
CCIO
= Max.
V
OUT
= 0.5V
–10
–10
10
10
–10
–10
10
10
–10
–10
10
10
μA
μA
I
OS[8]
Output Short Circuit Current
–160
–160
–160
μA
I
BHL
Input Bus Hold LOW Sustaining Current V
CC
= Min.
V
PIN
= V
IL
+40
+30
+25
μA
I
BHH
Input Bus Hold HIGH Sustaining Current V
CC
= Min.
V
PIN
= V
IH
–40
–30
–25
μA
I
BHLO
I
BHHO
I
CC0
Input Bus Hold LOW Overdrive Current V
CC
= Max.
Input Bus Hold HIGH Overdrive Current V
CC
= Max.
Standby Current
+250
–250
All bins
20
20
30
60
60
+200
–200
All bins
20
20
30
60
60
+150
–150
μA
μA
μA
39K30
39K50
39K100
39K165
39K200
–125 bin
3
3
5
10
10
–83 bin
12
12
20
40
40
Pins
B4, C2
B8, G9
F11, J11
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY39200V256-233BBI | CPLDs at FPGA Densities |
| CY39200V256-233BGC | CPLDs at FPGA Densities |
| CY39200V256-233BGI | CPLDs at FPGA Densities |
| CY39200V256-233MBC | CPLDs at FPGA Densities |
| CY39200V256-233MBI | CPLDs at FPGA Densities |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY39200V256-233MGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V256-233MGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V256-233NTC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V388-125MGC | 功能描述:IC CPLD 200K GATE 388-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Delta 39K™ ISR™ 標(biāo)準(zhǔn)包裝:40 系列:ispMACH® 4000C 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):5.0ns 電壓電源 - 內(nèi)部:1.65 V ~ 1.95 V 邏輯元件/邏輯塊數(shù)目:32 宏單元數(shù):512 門數(shù):- 輸入/輸出數(shù):128 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:176-LQFP 供應(yīng)商設(shè)備封裝:176-TQFP（24x24） 包裝:托盤 |
| CY39200V388-181MGC | 制造商:Cypress Semiconductor 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。