參數(shù)資料
型號(hào): CY39200V208-125NTXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: PLD
英文描述: LOADABLE PLD, 10 ns, PQFP208
封裝: 28 X 28 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, EQFP-208
文件頁數(shù): 29/86頁
文件大?。?/td> 2802K
代理商: CY39200V208-125NTXC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *I
Page 35 of 86
Channel Memory Synchronous FIFO Programmable Flag Timing
Switching Waveforms (continued)
tCHMCLK
tCHMFS
tCHMFH
PORT B CLOCK
PROGRAMMABLE
WRITE ENABLE
ALMOST EMPTY FLAG
PORT A CLOCK
tCHMSKEW3
tCHMFO
READ ENABLE
(active LOW)
tCHMFS
tCHMFH
tCHMCLK
PORT B CLOCK
PROGRAMMABLE
WRITE ENABLE
ALMOST FULL FLAG
PORT A CLOCK
tCHMSKEW3
tCHMFO
READ ENABLE
(Active LOW)
相關(guān)PDF資料
PDF描述
CY39050V208-125NTXC LOADABLE PLD, 10 ns, PQFP208
CY39050V208-125NTXI LOADABLE PLD, 10 ns, PQFP208
CY39050V208-233NTXC LOADABLE PLD, 7.2 ns, PQFP208
CY39050V208-83NTXC LOADABLE PLD, 15 ns, PQFP208
CY39050V208-83NTXI LOADABLE PLD, 15 ns, PQFP208
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY39200V208-181BBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200V208-181BBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200V208-181BGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200V208-181BGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200V208-181MBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities