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      參數(shù)資料
      

      


      


      
型號(hào)：
CY39165Z256-181MGC

      

      
廠商：
Cypress Semiconductor Corp.

      

      
英文描述：
CPLDs at FPGA Densities

      

      
中文描述：
CPLD器件在FPGA的密度

      

      
文件頁(yè)數(shù)：
18/86頁(yè)

      

      
文件大?。?/td>
1212K

      

      
代理商：
CY39165Z256-181MGC


      

      

      

	
      
    
    

    
      
	
      Delta39K ISR
      CPLD Family
      Document #: 38-03039 Rev. *H
      Page 18 of 86 
      Switching Characteristics — Parameter Descriptions 
      Over the Operating Range
      [13]
      Parameter
      Combinatorial Mode Parameters
      Delay from any pin input, through any cluster on the channel associated with that pin input, to any pin output on the 
      horizontal or vertical channel associated with that cluster
      t
      EA
      Global control to output enable
      t
      ER
      Global control to output disable
      Asynchronous macrocell RESET or PRESET recovery time from any pin input on the horizontal or vertical channel 
      associated with the cluster the macrocell is in
      Asynchronous macrocell RESET or PRESET from any pin input on the horizontal or vertical channel associated 
      with the cluster that the macrocell is in to any pin output on those same channels
      Asynchronous macrocell RESET or PRESET minimum pulse width, from any pin input to a macrocell in the farthest 
      cluster on the horizontal or vertical channel the pin is associated with 
      Synchronous Clocking Parameters
      Set-up time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a 
      global clock
      Hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a 
      global clock
      Global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated with the 
      cluster that macrocell is in
      t
      IOS
      Set-up time of any input pin to the I/O cell register associated with that pin, relative to a global clock
      t
      IOH
      Hold time of any input pin to the I/O cell register associated with that pin, relative to a global clock
      t
      IOCO
      Clock to output of an I/O cell register to the output pin associated with that register
      t
      SCS
      Macrocell clock to macrocell clock through array logic within the same cluster
      t
      SCS2
      Macrocell clock to macrocell clock through array logic in different clusters on the same channel
      t
      ICS
      I/O register clock to any macrocell clock in a cluster on the channel the I/O register is associated with
      Macrocell clock to any I/O register clock on the horizontal or vertical channel associated with the cluster that the 
      macrocell is in
      t
      CHZ
      Clock to output disable (high-impedance)
      t
      CLZ
      Clock to output enable (low-impedance)
      f
      MAX
      Maximum frequency with internal feedback—within the same cluster
      Maximum frequency with internal feedback—within different clusters at the opposite ends of a horizontal or vertical 
      channel
      Product Term Clock
      t
      MCSPT
      Set-up time for macrocell used as input register, from input to product term clock
      t
      MCHPT
      Hold time of macrocell used as an input register
      t
      MCCOPT
      Product term clock to output delay from input pin
      t
      SCS2PT
      Register to register delay through array logic in different clusters on the same channel using a product term clock
      Channel Interconnect Parameters
      t
      CHSW
      Adder for a signal to switch from a horizontal to vertical channel and vice-versa
      t
      CL2CL
      Cluster-to-cluster delay adder (through channels and channel PIM)
      Miscellaneous Delays
      Delay from the input of a cluster PIM, through a macrocell in the cluster, back to a cluster PIM input. This parameter 
      can be added to the t
      PD
       and t
      SCS
       parameters for each extra pass through the AND/OR array required by a given 
      signal path
      t
      MCCD
      Adder for carry chain logic per macrocell
      t
      IOD
      Delay from the input of the output buffer to the I/O pin
      t
      IOIN
      Delay from the I/O pin to the input of the channel buffer
      Note:
      13. Add t
      CHSW
       to signals making a horizontal to vertical channel switch or vice-versa.
      Description
      t
      PD
      t
      PRR
      t
      PRO
      t
      PRW
      t
      MCS
      t
      MCH
      t
      MCCO
      t
      OCS
      f
      MAX2
      t
      CPLD
      
    
      
    
    
      


      


      

      相關(guān)PDF資料
      		

      PDF描述
      		

      
      

      
CY39200Z256-181MGC
CPLDs at FPGA Densities

      

      
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WIRE STRIPPER, 0.25MMWIRE STRIPPER, 0.25MM; Stripping Capacity:0.25mm

      

      

      

      


      


      

      相關(guān)代理商/技術(shù)參數(shù)
      		

      參數(shù)描述
      		

      
      

      
CY39165Z256-181NC
 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities

      

      
CY39165Z256-200MGC
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CY39165Z256-233MGC
 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities

      

      
CY39165Z256-233MGI
 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities

      

      
CY39165Z256-233NTC
 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities

      

      
    
    
    
	
      	
    
    
     
     
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