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      參數(shù)資料
      

      


      


      
型號：
CY39050V208-233MGC

      

      
廠商：
Cypress Semiconductor Corp.

      

      
英文描述：
CPLDs at FPGA Densities

      

      
中文描述：
CPLD器件在FPGA的密度

      

      
文件頁數(shù)：
86/86頁

      

      
文件大?。?/td>
1235K

      

      
代理商：
CY39050V208-233MGC


      

      

      

	
      
    
    

    
      
	
      Delta39K ISR
      CPLD Family
      Document #: 38-03039 Rev. *H
      Page 86 of 86 
      Document History Page
      Document Title: Delta39K ISR CPLD Family CPLDs at FPGA Densities
      Document Number: 38-03039
      Issue 
      Date
      Change
      **
      106503
      05/30/01
      SZV
      *A
      107625
      07/11/01
      RN
      REV.
      ECN NO.
      Orig. of 
      Description of Change
      Change from Spec #: 38-00830 to 38-03039
      Deleted 39K15 device and the associated -250-MHz bin specs
      Deleted 144FBGA package and associated part numbers
      Changed ESD spec from “MIL-STD-883” to “JEDEC EIA/JESD22-A114-A”
      Changed the Prime bin for 39K50 and 39K30 from “MHz” to “233 MHz”
      Changed the part ordering information accordingly
      Updated the -233-MHz timing specs to match modified timing specs achieved by 
      design (main affected params: t
      PD
      , t
      MCCO
      , t
      IOS
      , t
      SCS
      , t
      SCS2
      , f
      MAX2
      , t
      CLMAA
      , 
      t
      CLMCYC2
      , t
      CHMCYC2
      , t
      CHMCLK
      )
      Updated I/O standard Timing Delay Specs and changed the default I/O standard 
      from 3.3V PCI to LVCMOS
      Added paragraph about Delta39K being CompactPCI hot swap Ready
      Added X8 mode in the PLL description
      Added Standby ICC spec
      Updated the recommended boot PROM for 39K165/200 to be CY3LV002 instead 
      of CY3LV020
      Updated Delta39K family offering
      Modified PLL timing parameters t
      DWSA
      , t
      DWOSA
      , t
      MCCJ
      , and t
      LOCK
      . Added t
      INDUTY
      parameter
      Deleted exception to CompactPCI Hot Swap compliance regarding “PCI 
      buffers....”
      Added reference to app note “Hot Socketing Delta39K”
      Revised CompactPCI Hot Swap Specification R1.0 to be R2.0
      Combined with spec# 38-03040
      Updated pin tables for 39K30 (208PQFP, 256FBGA)
      Updated pin tables for 39K50 (208PQFP, 256/484FBGA, 388BGA)
      Added X3, X5, X6, X16 multiplication modes to Spread Aware PLL
      Added PLL parameters (f
      PLLVCO
      , P
      SAPLLI
      , f
      MPPLI
      )
      Added and updated Storage Temperature for 39K200-208EQFP
      Changed the I
      cc0
       spec for 39K165 and 39K200 
      Updated tCLZ, tCHMCYC2 parameter Values for -233 MHz bin
      Updated 
      Input and Output Standard Timing Delay Adjustment 
      table
      Removed Self Boot Industrial parts from the offering
      Removed Delta39K165Z (1.8V) from the offering
      Removed 144-FBGA package offering
      Added self-boot Flash Memory endurance and data retention data 
      Added Family, Package, and Density Migration section 
      Added note 20 to 484/676 FBGA pin table to identify slow 39K165 IOs 
      Changed data sheet status from Preliminary to Final 
      Added note 7 to DC Characteristics
      Updated spec 51-85103 (MG388 package drawing) to rev. *C
      Changed the definition of following pins on CY39030 -256FBGA package:
      Pin A10: From 
      IO/Vref7
       to 
      IO/Vref6
      Pin B7: From 
      IO/Vref6
       to 
      V
      CC
      Added Table to identify Bank Location of Global Clock and Global Control Pins
      Removed all “Z” parts (1.8V)
      Referenced EEPROM to ATMEL part number
      *B
      109681
      11/16/01
      RN
      *C
      *D
      112376
      112946
      12/21/01
      04/04/02
      RN
      RN
      *E
      117518
      10/04/02
      OOR
      *F
      *G
      121063
      122543
      11/06/02
      12/10/02
      DSG
      RN
      *H
      128684
      08/04/03
      OOR
      
    
      
    
    
      


      


      

      相關(guān)PDF資料
      		

      PDF描述
      		

      
      

      
CY39050V208-233MGI
CPLDs at FPGA Densities

      

      
CY39050V208-233NC
CPLDs at FPGA Densities

      

      
CY39050V208-233NI
CPLDs at FPGA Densities

      

      
CY39050Z256-125BGC
CPLDs at FPGA Densities

      

      
CY39050Z256-125BGI
CPLDs at FPGA Densities

      

      

      

      


      


      

      相關(guān)代理商/技術(shù)參數(shù)
      		

      參數(shù)描述
      		

      
      

      
CY39050V208-233NTXC
功能描述:IC CPLD 50K GATE 208BQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Delta 39K™ ISR™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤

      

      
CY39050V208-83NTXC
功能描述:IC CPLD 50K GATE 208BQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Delta 39K™ ISR™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤

      

      
CY39050V208-83NTXI
功能描述:IC CPLD 50K GATE 208BQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Delta 39K™ ISR™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤

      

      
CY39050V484-125BBC
 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities

      

      
CY39050V484-125BBI
 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities

      

      
    
    
    
	
      	
    
    
     
     
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