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參數(shù)資料
| 型號： | CY39030Z388-125BGC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | CPLDs at FPGA Densities |
| 中文描述： | CPLD器件在FPGA的密度 |
| 文件頁數(shù)： | 14/86頁 |
| 文件大?。?/td> | 1235K |
| 代理商： | CY39030Z388-125BGC |
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Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 14 of 86
IEEE 1149.1-compliant JTAG Operation
The Delta39K family has an IEEE 1149.1 JTAG interface for
both Boundary Scan and ISR operations.
Four dedicated pins are reserved on each device for use by
the Test Access Port (TAP).
Boundary Scan
The Delta39K family supports Bypass, Sample/Preload,
Extest, Intest, Idcode and Usercode boundary scan instruc-
tions. The JTAG interface is shown in
Figure 11
.
In-System Reprogramming (ISR)
In-System Reprogramming is the combination of the capability
to program or reprogram a device on-board, and the ability to
support design changes without changing the system timing
or device pinout. This combination means design changes
during debug or field upgrades do not cause board respins.
The Delta39K family implements ISR by providing a JTAG
compliant interface for on-board programming, robust routing
resources for pinout flexibility, and a simple timing model for
consistent system performance.
Configuration
Each device of the Delta39K family is available in a volatile and
a Self-Boot package. Cypress’s CPLD boot EEPROM is used
to store configuration data for the volatile solution and an
embedded on-chip FLASH memory device is used for the Self-
Boot solution.
For volatile Delta39K packages, programming is defined as
the loading of a user’s design into the external CPLD boot
EEPROM. For Self-Boot Delta39K packages, programming is
defined as the loading of a user’s design into the on-chip
FLASH internal to the Delta39K package. Configuration is
defined as the loading of a user’s design into the Delta39K die.
Channel
RAM
4
GCLK[3:0]
LB 0
PIM
RAM
LB 5
LB 4
RAM
LB 6
LB 7
LB 2
LB 3
Cluster
LB 1
Channel
RAM
4
LB 0
PIM
RAM
LB 5
LB 4
RAM
LB 6
LB 7
LB 2
LB 3
LB 1
Channel
RAM
4
LB 0
PIM
RAM
LB 5
LB 4
RAM
LB 6
LB 7
LB 2
LB 3
LB 1
Channel
RAM
4
LB 0
PIM
8 Kb
LB 5
LB 4
8 Kb
LB 6
LB 7
LB 2
LB 3
LB 1
Channel
RAM
4
GCLK[3:0]
LB 0
PIM
RAM
LB 5
LB 4
RAM
LB 6
LB 7
LB 2
LB 3
LB 1
4
LB 0
PIM
LB 5
LB 4
RAM
LB 6
LB 7
LB 2
LB 3
RAM
LB 1
4
LB 0
PIM
RAM
LB 5
LB 4
RAM
LB 6
LB 7
LB 2
LB 3
LB 1
Channel
RAM
4
LB 0
PIM
RAM
LB 5
LB 4
Cluster
RAM
LB 6
LB 7
LB 2
LB 3
LB 1
Channel
RAM
4
GCLK[3:0]
LB 0
PIM
RAM
LB 5
LB 4
RAM
LB 6
LB 7
LB 2
LB 3
LB 1
Channel
RAM
4
LB 0
PIM
RAM
LB 5
LB 4
RAM
LB 6
LB 7
LB 2
LB 3
LB 1
Channel
RAM
4
LB 0
PIM
RAM
LB 5
LB 4
RAM
LB 6
LB 7
LB 2
LB 3
LB 1
Channel
RAM
4
LB 0
PIM
RAM
LB 5
LB 4
RAM
LB 6
LB 7
LB 2
LB 3
LB 1
Channel
RAM
Channel
RAM
t
MCS
t
PD
t
SCS
t
MCCO
t
SCS2
Figure 10. Timing Model for 39K100 Device
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| CY39030Z388-125BGI | CPLDs at FPGA Densities |
| CY39030Z388-125MBC | CPLDs at FPGA Densities |
| CY39030Z388-125MBI | CPLDs at FPGA Densities |
| CY39030Z388-125MGC | CPLDs at FPGA Densities |
| CY39030Z388-125MGI | CPLDs at FPGA Densities |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CY39030Z484-125BBC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39030Z484-125BBI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39030Z676-125BBC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39030Z676-125BBI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39030Z676-125BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
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