參數(shù)資料
型號： CY38050V256-83BBC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： LOADABLE PLD, 15 ns, PBGA256
封裝： 17 X 17 MM, FBGA-256
文件頁數(shù)： 1/45頁
文件大?。?/td> 720K
代理商： CY38050V256-83BBC
CPLDs Designed for Migration
Quantum38K ISR
CPLD Family
USE DELTA39K FOR
ALL NEW DESIGNS
Cypress Semiconductor Corporation
3901 North First Street
San Jose
, CA 95134
408-943-2600
Document #: 38-03043 Rev. *G
Revised April 18, 2003
Features
High density
— 30K to 100K usable gates
— 512 to 1536 macrocells
— 136 to 302 maximum I/O pins
— Eight dedicated inputs including four clock pins and
four global I/O control signal pins; four JTAG inter-
face pins for reconfigurability/boundary scan
Embedded memory
— 16-Kb to 48-Kb embedded dual-port channel memo-
ry
125-MHz in-system operation
AnyVolt interface
— 3.3V and 2.5V VCC operation
— 3.3V, 2.5V and 1.8V I/O capability
Low-power operation
— 0.18-mm 6-layer metal SRAM-based logic process
— Full-CMOS implementation of product term array
Simple timing model
— No penalty for using full 16 product terms/macrocell
— No delay for single product term steering or sharing
Flexible clocking
— Four synchronous clocks per device
— Locally generated product term clock
— Clock polarity control at each register
Carry-chain logic for fast and efficient arithmetic opera-
tions
Multiple I/O standards supported
— LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI
Compatible with NoBL, ZBT, and QDR SRAMs
Programmable slew rate control on each I/O pin
User-programmable Bus Hold capability on each I/O pin
Fully 3.3V PCI-compliant (as per PCI spec rev. 2.2)
Compact PCI hot swap ready
Multiple package/pinout offering across all densities
— 208 to 484 pins in PQFP and FBGA packages
— Simplifies design migration across density
In-System Reprogrammable (ISR)
— JTAG-compliant on-board configuration
— Design changes do not cause pinout changes
IEEE1149.1 JTAG boundary scan
Pin-to-pin-compatible with Cypress’s high-end
Delta39K CPLDs allowing easy migration path to
— More embedded memory
— Spread Aware PLL
— Higher density and higher speed devices
— High speed I/O standards and more
Development Software
Warp
— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing
— Active-HDL FSM graphical finite state machine editor
— Active-HDL SIM post-synthesis timing simulator
— Architecture Explorer for detailed design analysis
— Static Timing Analyzer for critical path analysis
— Available on Windows 98, Windows NT,
Windows ME, Windows 2000, and Sun Solaris
2.5 and later for $99
— Supports all Cypress programmable logic products
Notes:
1.
Upper limit of typical gates is calculated by assuming that only 50% of the channel memory is used.
2.
Standby ICC values are with no output load and stable inputs.
Quantum38K
ISR CPLD Family Members
Device
Typical Gates[1]
Macrocells
Channel
memory
(Kb)
MaximumI/O
Pins
fMAX2
(MHz)
Speed — tPD
Pin-to-Pin
(ns)
Standby ICC
[2]
TA=25×C
3.3/2.5V
38K30
16K–48K
512
16
174
125
10
5 mA
38K50
23K–72K
768
24
218
125
10
5 mA
38K100
46K–144K
1536
48
302
125
10
10 mA
相關PDF資料
PDF描述
CY38050V484-83BBC LOADABLE PLD, 15 ns, PBGA484
CY38050V208-125NC LOADABLE PLD, 10 ns, PQFP208
CY38050V208-125NI LOADABLE PLD, 10 ns, PQFP208
CY38050V256-125BBC LOADABLE PLD, 10 ns, PBGA256
CY38050V256-125BBI LOADABLE PLD, 10 ns, PBGA256
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