
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *D
Page 25 of 64
CY37064
CY37128
Typical 5.0V Power Consumption
(continued)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 5.0V, T
A
= Room Temperature
0
10
20
30
40
50
60
70
80
90
0
20
40
60
80
100
120
140
160
180
Frequency (MHz)
I
Low Power
High Speed
0
20
40
60
80
100
120
140
160
0
20
40
60
80
100
120
140
160
180
Frequency (MHz)
I
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 5.0V, T
A
= Room Temperature