
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *D
Page 29 of 64
CY37128V
CY37192V
Typical 3.3V Power Consumption
(continued)
0
10
20
30
40
50
60
70
80
0
20
40
60
Frequency (M H z)
80
100
120
140
I
Low Power
H igh Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 3.3V, T
A
= Room Temperature
0
20
40
60
80
100
120
0
20
40
60
80
100
120
F re q u en c y (M H z)
I
Low P ow er
H igh S peed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 3.3V, T
A
= Room Temperature