參數(shù)資料
型號(hào)： CY37128VP44-83UXC
廠商： Cypress Semiconductor Corp.
英文描述： 5V, 3.3V, ISRTM High-Performance CPLDs
中文描述： 為5V，3.3V，ISRTM高性能的CPLD
文件頁數(shù)： 18/64頁
文件大?。?/td> 1792K
代理商： CY37128VP44-83UXC
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *D
Page 18 of 64
Product Term Clocking Parameters
t
COPT[13, 14, 15]
t
SPT
t
HPT
t
ISPT[13]
Product Term Clock or Latch Enable (PTCLK) to Output
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)
Register or Latch Data Hold Time
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or
Latch Enable (PTCLK)
Buried Register Used as an Input Register or Latch Data Hold Time
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)
Pipelined Mode Parameters
t
ICS[13]
Input Register Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) to Output Register Synchronous
Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
)
Operating Frequency Parameters
f
MAX1
f
MAX2
Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(t
WL
+ t
WH
),
1/(t
S
+ t
H
), or 1/t
CO
)
[5]
f
MAX3
f
MAX4
Maximum Frequency in Pipelined Mode (Lesser of 1/(t
CO
+ t
IS
), 1/t
ICS
, 1/(t
WL
+ t
WH
), 1/(t
IS
+ t
IH
),
or 1/t
SCS
)
[5]
Reset/Preset Parameters
t
RW
t
RR[13]
t
RO[13, 14, 15]
Asynchronous Reset to Output
t
PW
t
PR[13]
t
PO[13, 14, 15]
Asynchronous Preset to Output
User Option Parameters
t
LP
Low Power Adder
t
SLEW
Slow Output Slew Rate Adder
t
3.3IO
JTAG Timing Parameters
t
S JTAG
t
H JTAG
t
CO
JTAG
f
JTAG
ns
ns
ns
ns
t
IHPT
t
CO2PT[13, 14, 15]
ns
ns
ns
Maximum Frequency with Internal Feedback (Lesser of 1/t
SCS
, 1/(t
S
+ t
H
), or 1/t
CO
)
[5]
MHz
MHz
Maximum Frequency with External Feedback (Lesser of 1/(t
CO
+ t
S
) or 1/(t
WL
+ t
WH
)
[5]
MHz
MHz
Asynchronous Reset Width
[5]
Asynchronous Reset Recovery Time
[5]
ns
ns
ns
ns
ns
ns
Asynchronous Preset Width
[5]
Asynchronous Preset Recovery Time
[5]
ns
ns
ns
3.3V I/O Mode Timing Adder
[5]
Set-up Time from TDI and TMS to TCK
[5]
Hold Time on TDI and TMS
[5]
Falling Edge of TCK to TDO
[5]
Maximum JTAG Tap Controller Frequency
[5]
ns
ns
ns
ns
Switching Characteristics
Over the Operating Range (continued)
[12]
Parameter
Description
Unit
相關(guān)PDF資料
PDF描述
CY37128VP48-100AXC 5V, 3.3V, ISRTM High-Performance CPLDs
CY37128VP48-167NXC 5V, 3.3V, ISRTM High-Performance CPLDs
CY37128VP48-200AXC 5V, 3.3V, ISRTM High-Performance CPLDs
CY37128VP48-200BAXC 5V, 3.3V, ISRTM High-Performance CPLDs
CY37128VP48-200NTXC 5V, 3.3V, ISRTM High-Performance CPLDs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY37128VP44-83YXC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs
CY37128VP48-100AXC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs
CY37128VP48-100BAXC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs
CY37128VP48-100BBXC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs
CY37128VP48-100BGXC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*