
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *D
Page 30 of 64
CY37256V
CY37384V
Typical 3.3V Power Consumption
(continued)
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120
F req u e n c y (M H z)
I
Low P ow er
H igh S peed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 3.3V, T
A
= Room Temperature
0
20
40
60
80
100
120
140
160
180
200
0
10
20
30
40
50
60
70
80
90
Frequency (M Hz)
I
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 3.3V, T
A
= Room Temperature