參數(shù)資料
型號(hào)： CY37032P44-125AC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： 5V, 3.3V, ISRTM High-Performance CPLDs
中文描述： EE PLD, 10 ns, PQFP44
封裝： PLASTIC, TQFP-44
文件頁數(shù)： 18/64頁
文件大?。?/td> 1798K
代理商： CY37032P44-125AC
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *D
Page 18 of 64
Product Term Clocking Parameters
t
COPT[13, 14, 15]
t
SPT
t
HPT
t
ISPT[13]
Product Term Clock or Latch Enable (PTCLK) to Output
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)
Register or Latch Data Hold Time
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or
Latch Enable (PTCLK)
Buried Register Used as an Input Register or Latch Data Hold Time
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)
Pipelined Mode Parameters
t
ICS[13]
Input Register Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) to Output Register Synchronous
Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
)
Operating Frequency Parameters
f
MAX1
f
MAX2
Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(t
WL
+ t
WH
),
1/(t
S
+ t
H
), or 1/t
CO
)
[5]
f
MAX3
f
MAX4
Maximum Frequency in Pipelined Mode (Lesser of 1/(t
CO
+ t
IS
), 1/t
ICS
, 1/(t
WL
+ t
WH
), 1/(t
IS
+ t
IH
),
or 1/t
SCS
)
[5]
Reset/Preset Parameters
t
RW
t
RR[13]
t
RO[13, 14, 15]
Asynchronous Reset to Output
t
PW
t
PR[13]
t
PO[13, 14, 15]
Asynchronous Preset to Output
User Option Parameters
t
LP
Low Power Adder
t
SLEW
Slow Output Slew Rate Adder
t
3.3IO
JTAG Timing Parameters
t
S JTAG
t
H JTAG
t
CO
JTAG
f
JTAG
ns
ns
ns
ns
t
IHPT
t
CO2PT[13, 14, 15]
ns
ns
ns
Maximum Frequency with Internal Feedback (Lesser of 1/t
SCS
, 1/(t
S
+ t
H
), or 1/t
CO
)
[5]
MHz
MHz
Maximum Frequency with External Feedback (Lesser of 1/(t
CO
+ t
S
) or 1/(t
WL
+ t
WH
)
[5]
MHz
MHz
Asynchronous Reset Width
[5]
Asynchronous Reset Recovery Time
[5]
ns
ns
ns
ns
ns
ns
Asynchronous Preset Width
[5]
Asynchronous Preset Recovery Time
[5]
ns
ns
ns
3.3V I/O Mode Timing Adder
[5]
Set-up Time from TDI and TMS to TCK
[5]
Hold Time on TDI and TMS
[5]
Falling Edge of TCK to TDO
[5]
Maximum JTAG Tap Controller Frequency
[5]
ns
ns
ns
ns
Switching Characteristics
Over the Operating Range (continued)
[12]
Parameter
Description
Unit
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY37032P44-125ACT 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs
CY37032P44-125AI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISR⑩ High-Performance CPLDs
CY37032P44-125AXC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 32 Macrocell 5V COM RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
CY37032P44-125AXCT 功能描述:CPLD - 復(fù)雜可編程邏輯器件 32 Macrocell 5V COM RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
CY37032P44-125JC 制造商:Cypress Semiconductor 功能描述:
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