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參數(shù)資料
| 型號(hào)： | CY2V995AIT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | S2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer |
| 中文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP44 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, PLASTIC, TQFP-44 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 281K |
| 代理商： | CY2V995AIT |
2.5/3.3V 200-MHz Multi-Output
Zero Delay Buffer
CY2V995
Cypress Semiconductor Corporation
Document #: 38-07435 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 19, 2004
Features
2.5V or 3.3V operation
Split output bank power supplies
Output frequency range: 6 MHz to 200 MHz
Output-output skew: < 150 ps
Cycle-cycle jitter: < 100 ps
Selectable positive or negative edge synchronization
8 LVTTL outputs driving 50
terminated lines
LVCMOS/LVTTL over-voltage tolerant reference input
Selectable phase-locked loop (PLL) frequency range
and lock indicator
(1-6,8,10,12)x multiply and (1/2,1/4)x divide ratios
Spread-Spectrum-compatible
Power-down mode
Industrial temperature range: –40
°
C to +85
°
C
44-pin TQFP package
Description
The CY2V995 is a low-voltage, low-power, eight output,
200-MHz clock driver. It features function necessary to
optimize the timing of high-performance computer and
communication systems.
The user can program the frequency of the output banks
through nF[0:1] and DS[0:1] pins. Any one of the outputs can
be connected to feedback input to achieve different reference
frequency multiplication and divide ratios and zero
input-output delay.
The device also features split output bank power supplies
which enable the user to run two banks (1Qn and 2Qn) at a
power supply level different from that of the other two banks
(3Qn and 4Qn). Additionally, the PE pin controls the synchro-
nization of the output signals to either the rising or the falling
edge of the reference clock.
Block Diagram
Pin Configuration
PE
TEST
FS
3
3
REF
FB
2F1:0
1F1:0
3F1:0
4F1:0
1Q0
1Q1
2Q0
2Q1
3Q0
3Q1
4Q0
4Q1
PLL
3
3
3
3
/K
sOE#
VDDQ1
VDDQ4
LOCK
/N
3
3
PD#
DS1:0
/M
VDDQ3
CY2V995
44 43 42 41 40 39 38 37 36 35 34
12 13 14 15 16 17 18 19 20 2122
4F1
sOE#
PD#
PE
VDDQ4
VDDQ4
4Q1
4Q0
VSS
VSS
VSS
V
3
3
V
V
F
V
V
2
2
V
4
3
3
F
V
R
V
T
2
2
1
1F0
DS1
DS0
LOCK
VDDQ1
VDDQ1
1Q0
1Q1
VSS
VSS
VSS
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
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