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參數(shù)資料
| 型號： | CY2SSTV850ZI |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIFFDRV PLL DDR 48TSSOP |
| 標準包裝： | 39 |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 170MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應商設備封裝： | * |
| 包裝： | * |
CY2SSTV850
......................... Document #: 38-07457 Rev. *A Page 2 of 9
Notes:
1. PU= internal pull-up
2. A bypass capacitor (0.1
F) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces
Pin Description[1, 2]
Pin
Name
I/O
Description
Electrical Characteristics
13
CLKINT
I
Complementary Clock Input.
LV Differential Input
14
CLKINC
I
Complementary Clock Input.
35
FBINC
I
Feedback Clock Input. Connect to FBOUTC for
accessing the PLL.
Differential Input
36
FBINT
I
Feedback Clock Input. Connect to FBOUTT for
accessing the PLL.
3, 5, 10, 20, 22
46, 44, 39, 29,27
YT(0:9)
O
Clock Outputs
Differential Outputs
2, 6, 9, 19, 23
47, 43, 40,30,26
YC(0:9)
O
Clock Outputs
32
FBOUTT
O
Feedback Clock Output. Connect to FBINT for
normal operation. A bypass delay capacitor at
this output will control Input Reference/Output
Clocks phase relationships.
Differential Outputs
33
FBOUTC
O
Feedback Clock Output. Connect to FBINC for
normal operation. A bypass delay capacitor at
this output will control Input Reference/Output
Clocks phase relationships.
12
SCLK
I, PU
Serial Clock Input. Clocks data at SDATA into
the internal register.
Data Input for the two-line serial
bus
37
SDATA
I/O, PU Serial Data Input. Input data is clocked to the
internal register to enable/disable individual
outputs. This provides flexibility in power
management.
Data Input and Output for the
two-line serial bus
11
VDD
2.5V power Supply for Logic
2.5V Nominal
4, 21, 28, 34, 38, 45 VDDQ
2.5V Power Supply for Output Clock Buffers 2.5V Nominal
16
AVDD
2.5V Power Supply for PLL
2.5V Nominal
15
VDDI
Power Supply for two-line serial Interface
2.5V or 3.3V Nominal
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
VSS
Common Ground
0.0V Ground
17
AVSS
Analog Ground
0.0V Analog Ground
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY2SSTV850ZIT | 功能描述:時鐘緩沖器 DDR1 Clock PLL RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY2SSTV855 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Differential Clock Buffer/Driver |
| CY2SSTV855_06 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Differential Clock Buffer/Driver |
| CY2SSTV855ZC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Differential Clock Buffer/Driver |
| CY2SSTV855ZCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Differential Clock Buffer/Driver |
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