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參數(shù)資料
| 型號： | CY2PP326 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 246K |
| 代理商： | CY2PP326 |
PRELIMINARY
FastEdge Series
CY2PP3115
Document #: 38-07502 Rev.*A
Page 5 of 12
Timing Definitions
Note:
19. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |.
tsk
(PP)
Output-to-output skew (part-to-part)
50% duty cycle Standard load Differential
Operation
–
200
ps
T
JIT(CC)
Output cycle-to-cycle jitter (determin-
istic/Intrinsic)
All outputs /1
500 MHz 50% duty cycle Standard load Differ-
ential Operation
–
2
ps
Output cycle-to-cycle jitter (determin-
istic/Intrinsic)
All outputs /2
660 MHz 50% duty cycle Standard load Differ-
ential Operation
–
2
ps
Output cycle-to-cycle jitter (determin-
istic/Intrinsic)
All outputs Bank(A and C)/1, Bank(B and
D)/2
660 MHz 50% duty cycle Standard load Differ-
ential Operation
–
2
ps
Output cycle-to-cycle jitter (determin-
istic/Intrinsic)
All outputs Bank A/1, Bank(B,C and D)/2
Output pulse skew
[19]
660 MHz 50% duty cycle Standard load Differ-
ential Operation
–
2
ps
tsk
(P)
660 MHz 50% duty cycle Standard load Differ-
ential Operation
–
75
ps
T
R
,T
F
Output Rise / Fall time
660 MHz 50% duty cycle Differential 20% to
80%
–
0.3
ns
TTB
Total Timing Budget
500 MHz 50% duty cycle Standard load
–
250
ps
Table 2. TPD–Propagation Delay 66-MHz 50% Duty Cycle
TPD
FSELA
CLK_SEL
Unit
ns
ns
ns
ns
ns
ns
ns
ns
0
1
0
1
0
1
0
1
0
1
0.900
0.979
0.951
0.962
0.952
1.019
0.986
1.018
0.974
0.982
0.974
0.966
0.974
1.021
0.980
1.022
FSELB
FSELC
FSELD
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
VIH
VIL
VCMR
VPP
VCMR Min = 1.2V
VPP range
0.1V - 1.3V
VCMR Max = VCC
VCC = 2.5V or 3.3V
VCC
VEE
VEE = 0.0V
Figure 1. PECL Waveform Definitions
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2PP326AI | 功能描述:時鐘驅(qū)動器及分配 2.5V or 3.3V 1.5GHz IND RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CY2PP326AIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2 x 2 Clock and Data Switch Buffer |
| CY2S25-PS | 制造商:SMC Corporation of America 功能描述:Seal Kit for CY2S 25mm guided cylinder |
| CY2SSTU32864 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| CY2SSTU32864BFXC | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register |
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