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參數(shù)資料
| 型號(hào)： | CY29946 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2.5V or 3.3V, 200-MHz, 1:10 Clock Distribution Buffer |
| 中文描述： | 2.5V或3.3V，200兆赫，1:10時(shí)鐘分配緩沖區(qū) |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 111K |
| 代理商： | CY29946 |
2.5V or 3.3V, 200-MHz, 1:10 Clock Distribution Buffer
CY29946
Cypress Semiconductor Corporation
Document #: 38-07286 Rev. *E
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised April 22, 2004
Features
2.5V or 3.3V operation
200-MHz clock support
Two LVCMOS-/LVTTL-compatible inputs
Ten clock outputs: drive up to 20 clock lines
1× or 1/2× configurable outputs
Output three-state control
250-ps max. output-to-output skew
Pin-compatible with MPC946, MPC9446
Available in commercial and industrial temperature
range
32-pin TQFP package
Description
The CY29946 is a low-voltage 200-MHz clock distribution
buffer with the capability to select one of two LVCMOS/LVTTL
compatible input clocks. These clock sources can be used to
provide for test clocks as well as the primary system clocks.
All other control inputs are LVCMOS/LVTTL compatible. The
10 outputs are LVCMOS or LVTTL compatible and can drive
50
series or parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:20.
The CY29946 is capable of generating 1× and 1/2× signals
from a 1× source. These signals are generated and retimed
internally to ensure minimal skew between the 1× and 1/2×
signals. SEL(A:C) inputs allow flexibility in selecting the ratio
of 1× to1/2× outputs.
The CY29946 outputs can also be three-stated via MR/OE#
input. When MR/OE# is set HIGH, it resets the internal
flip-flops and three-states the outputs.
CY29946
M
V
Q
V
Q
V
Q
V
V
Q
V
Q
V
Q
V
Q
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
VDDC
TCLK_SEL
VDD
TCLK0
TCLK1
DSELA
DSELB
DSELC
VSS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
1
1
1
1
1
1
1
3
3
3
2
2
2
2
2
Block Diagram
Pin Configuration
0
1
/1
/2
R
0
1
/1
/2
R
0
1
/1
/2
R
3
3
4
QA0:2
QB0:2
QC0:3
DSELA
DSELB
DSELC
MR/OE#
TCLK1
TCLK0
TCLK_SEL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY29946AIXT | Circular Connector; No. of Contacts:5; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:10-5 RoHS Compliant: No |
| CY29946AXC | Cable Ties; Body Material:Nylon 6.6; Color:Black; Pack Quantity:1000 RoHS Compliant: Yes |
| CY29946AXCT | 2.5V or 3.3V, 200-MHz, 1:10 Clock Distribution Buffer |
| CY29946AXI | 2.5V or 3.3V, 200-MHz, 1:10 Clock Distribution Buffer |
| CY29947 | 2.5V or 3.3V, 200-MHz, 1:9 Clock Distribution Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY29946_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5 V or 3.3 V, 200-MHz, 1:10 Clock Distribution Buffer 200-MHz clock support |
| CY29946_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5 V or 3.3 V, 200-MHz, 1:10 Clock Distribution Buffer |
| CY29946AC | 制造商:Cypress Semiconductor 功能描述: |
| CY29946ACT | 制造商:Cypress Semiconductor 功能描述: |
| CY29946AI | 制造商:Cypress Semiconductor 功能描述:Clock Divider 2-IN LVCMOS/LVTTL 32-Pin TQFP |
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