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參數(shù)資料
| 型號： | CY29940 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
| 中文描述： | 2.5V或3.3V，200兆赫，1:18時(shí)鐘分配緩沖區(qū) |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 189K |
| 代理商： | CY29940 |
2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
CY29940
Cypress Semiconductor Corporation
Document #: 38-07283 Rev. *B
3901 North First Street
San Jose
CA 95134
Revised December 21, 2002
408-943-2600
40
Features
200-MHz clock support
LVPECL or LVCMOS/LVTTL clock input
LVCMOS/LVTTL compatible inputs
18 clock outputs: drive up to 36 clock lines
150 ps max. output-to-output skew
Dual or single supply operation:
—3.3V core and 3.3V outputs
—3.3V core and 2.5V outputs
—2.5V core and 2.5V outputs
Pin compatible with MPC940L, MPC9109
Available in Commercial and Industrial temperature
32-pin LQFP package
Description
The CY29940 is a low-voltage 200-MHz clock distribution buff-
er with the capability to select either a differential LVPECL or
a LVCMOS/LVTTL compatible input clock. The two clock
sources can be used to provide for a test clock as well as the
primary system clock. All other control inputs are LVC-
MOS/LVTTL compatible. The eighteen outputs are 2.5V or
3.3V LVCMOS/LVTTL compatible and can drive 50
series or
parallel terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:36. Low out-
put-to-output skews make the CY29940 an ideal clock distri-
bution buffer for nested clock trees in the most demanding of
synchronous systems.
Block Diagram
Pin Configuration
PECL_CLK
PECL_CLK#
0
1
TCLK
TCLK_SEL
VDDC
18
Q0-Q17
VDD
CY29940
Q
Q
Q
V
Q
Q
Q
V
Q
Q
Q
V
Q
Q
Q
V
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
VSS
VSS
TCLK
TCLK_SEL
PECL_CLK
PECL_CLK#
VDD
VDDC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
1
1
1
1
1
1
1
3
3
3
2
2
2
2
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY29940AC | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
| CY29940ACT | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
| CY29940AI | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
| CY29940AIT | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
| CY29942 | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer(2.5V/3.3V, 200MHz, 1:18時(shí)鐘分配緩沖器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY29940_06 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
| CY29940_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5 V or 3.3 V, 200-MHz, 1:18 Clock Distribution Buffer 200-MHz clock support |
| CY2994-000 | 制造商:TE Connectivity 功能描述:CCK-ELKS-2/4-C - Bulk |
| CY29940-1 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V or 3.3V, 200-MHz 1:18 Clock Distribution Buffer |
| CY29940AC | 制造商:Cypress Semiconductor 功能描述:Clock Driver 2-IN LVCMOS/LVTTL 32-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:2.5V OR 3.3V, 200-MHZ, 1:18 CLOCK DISTRIBUTION BUFFER - Bulk |
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