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參數(shù)資料
| 型號(hào)： | CY28551LFXC-3 |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 6/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK INTEL/AMD SIS VIA 56QFN |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 類型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU，AMD CPU |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:20 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 400MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 56-QFN（8x8） |
| 包裝： | 托盤 |
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CY28551-3
....................Document #: 001-05677 Rev. *D Page 14 of 28
Associated Register Bits
CPU_DAF Enable – This bit enables CPU DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the CPU_DAF_N
register. Note: the CPU_DAF_N and M register must contain
valid values before CPU_DAF is set. Default = 0, (No DAF).
CPU_DAF_N – There are nine bits (for 512 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, (0000). The allowable values for N are detailed in the
frequency select table in Figure 1.
CPU DAF M – There are 7 bits (for 128 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, the allowable values for M are detailed in the frequency
select table in Figure 1.
SRC_DAF Enable – This bit enables SRC DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the SRC_DAF_N
register. Note: the SRC_DAF_N register must contain valid
values before SRC_DAF is set. Default = 0, (No DAF).
SRC_DAF_N – There are nine bits (for 512 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, (0000). The allowable values for N are detailed in the
frequency select table in Figure 1.
Recovery – The recovery mechanism during CPU DAF when
the system locks up and the watchdog timer is enabled is
determined
by
the
“Watchdog
Recovery
Mode”
and
“Watchdog Auto recovery Enable” bits. The possible recovery
methods are (A) Auto, (B) Manual (by Recovery N), (C) HW,
and (D) No recovery - just send reset signal.
There is no recovery mode for SRC Dial a frequency.
Software Frequency Select
This mode allows the user to select the CPU output
frequencies using the Software Frequency select bits in the
SMBUS register.
FSEL – There will be four bits (for 16 combinations) to select
predetermined CPU frequencies from a table. The table selec-
tions are detailed in Figure 1.
FS_Override – This bit allows the CPU frequency to be
selected from HW or FSEL settings. By default, this bit is not
set and the CPU frequency is selected by HW. When this bit
is set, the CPU frequency is selected by the FSEL bits. Default
= 0.
Recovery – The recovery mechanism during FSEL when the
system locks up is determined by the “Watchdog Recovery
Mode” and “Watchdog Auto recovery Enable” bits. The only
possible recovery method is to Hardware Settings. Auto
recovery or manual recovery can cause a wrong output
frequency because the output divider may have changed with
the selected CPU frequency and these recovery methods will
not recover the original output divider setting.
Smooth Switching
The device contains 1 smooth switch circuit that is shared by
the CPU PLL and SRC PLL. The smooth switch circuit ensures
that when the output frequency changes by overclocking, the
transition from the old frequency to the new frequency is a
slow, smooth transition containing no glitches. The rate of
change of output frequency when using the smooth switch
circuit is less than 1 MHz/0.667
s. The frequency overshoot
and undershoot will be less than 2%.
The Smooth Switch circuit can be assigned auto or manual. In
Auto mode, clock generator will assign smooth switch
automatically when the PLL will do overclocking. For manual
mode, the smooth switch circuit can be assign to either PLL
via Smbus. By default the smooth switch circuit is set to auto
mode. Either PLL can still be over-clocked when it does not
have control of the smooth switch circuit but it is not
guaranteed to transition to the new frequency without large
frequency glitches.
It is not recommended to enable over-clocking and change the
N values of both PLLs in the same SMBUS block write and use
smooth switch mechanism on spread spectrum on/off.
Watchdog Timer
The Watchdog timer is used in the system in conjunction with
overclocking. It is used to provide a reset to a system that has
hung up due to overclocking the CPU and the Front side bus.
The watchdog is enabled by the user and if the system
completes its checkpoints, the system will clear the timer.
However, when the timer runs out, there will be a reset pulse
generated on the SRESET# pin for 20 ms that is used to reset
the system.
When the Watchdog is enabled (WD_EN = 1) the Watchdog
timer will start counting down from a value of Watchdog_timer
* time scale. If the Watchdog timer reaches 0 before the
WD_EN bit is cleared then it will assert the SRESET# signal
and set the Watchdog Alarm bit to 1.
To use the watchdog the SRESET# pin must be enabled by
SRESET_EN pin being sampled LOW by VTTPWRGD#
assertion during system boot up.
At any point if during the Watchdog timer countdown, if the
time stamp or Watchdog timer bits are changed the timer will
reset and start counting down from the new value.
After the Reset pulse, the watchdog will stay inactive until
either:
1. A new time stamp or watchdog timer value is loaded.
2. The WD_EN bit is cleared and then set again.
Watchdog Register Bits
The following register bits are associated with the Watchdog
timer:
Watchdog Enable – This bit (by default) is not set, which
disables the Watchdog. When set, the Watchdog is enabled.
Also, when there is a transition from LOW to HIGH, the timer
reloads. Default = 0, disable
Watchdog Timer – There will be three bits (for seven combina-
tions) to select the timer value. Default = 000, the value '000'
is a reserved test mode.
Watchdog Alarm – This bit is a flag and when it is set, it
indicates that the timer has expired. This bit is not set by
default. When the bit is set, the user is allowed to clear. Default
= 0.
Watchdog Time Scale – This bit selects the multiplier. When
this bit is not set, the multiplier will be 250 ms. When set (by
default), the multiplier will be 3s. Default = 1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28551LFXC-3T | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Universal System Clk Intel AMD SiS Via RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28551LFXCT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Universal System Clk Intel AMD SiS Via RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY2862-000 | 制造商:TE Connectivity 功能描述:82A0111-4-9-G110 |
| CY2863-000 | 制造商:TE Connectivity 功能描述:82A0111-8-9-G110 - Bulk |
| CY28800 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Differential Buffer for PCI Express and SATA |
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