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參數(shù)資料
| 型號： | CY28447LFXCT |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Clock Generator for Intel㈢ Calistoga Chipset |
| 中文描述： | 時鐘發(fā)生器英特爾㈢Calistoga的芯片組 |
| 文件頁數(shù)： | 1/21頁 |
| 文件大?。?/td> | 210K |
| 代理商： | CY28447LFXCT |
PRELIMINARY
Clock Generator for Intel
Calistoga Chipset
CY28447
Rev
1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Page 1 of 21
Tel:(408) 855-0555
Fax:(408) 855-0550
www.SpectraLinear.com
Features
Compliant to Intel
CK410M
Selectable CPU frequencies
Differential CPU clock pairs
100 MHz differential SRC clocks
96 MHz differential dot clock
27 MHz Spread and Non-spread video clock
48 MHz USB clock
SRC clocks independently stoppable through
CLKREQ#[1:9]
96/100 MHz spreadable differential video clock
33 MHz PCI clocks
Buffered Reference Clock 14.318MHz
Low-voltage frequency select inputs
I
2
C support with readback capabilities
Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
3.3V power supply
72-pin QFN package
CPU
SRC
PCI
REF
DOT96
USB_48M
LCD
27M
x2 / x3
x9/11
x5
x 2
x 1
x 1
x1
x2
Pin Configuration
Block Diagram
C
C
S
S
V
S
S
V
S
S
C
S
S
S
S
C
S
S
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
VDD_SRC
SRCC_9
SRCT_9
VSS_SRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
VDD_SRC
SRCC_2
SRCT_2
SRCC_1
SRCT_1
VDD_SRC
SRCC_0 / LCD100MC
SRCT_0 / LCD100MT
CLKREQ1#
FSB/TEST_MODE
DOT96C / 27M_SS
DOT96T / 27M_NSS
VSS_48
48M / FSA
VDD_48
VTT_PWRGD# / PD
CLKREQ7#
PCIF0/ITP_SEL
CPUC2_ITP / SRCC_10
CPUT2_ITP / SRCT_10
VDDA
VSSA
IREF
CPUC1
CPUT1
VDD_CPU
CPUC0
CPUT0
VSS_CPU
SCLK
SDATA
VDD_REF
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
X
X
V
R
R
C
P
C
P
C
C
V
V
P
P
P
V
V
CY28447
IREF
VDD
CPUT[0:1]
CPUC[0:1]
REF[1:0]
VDD
CPUT2_ITP/SRCT10
CPUC2_ITP/SRCC10
VDD
VDD
Dvider
Dvider
Dvider
14.318MHz
Crystal
CPU
PLL
LVDS
PLL
Fixed
PLL
PLL Reference
XIN
XOUT
PCI_STP#
FS[C:A]
VTT_PWRGD#/PD
SRCT(1:9])
SRCC(1:9])
PCI[1:4]
VDD_PCI
VDD
PCIF0
VDD
SRCT0/100MT_SST
SRCC0/100MC_SST
VDD48
CPU_STP#
CLKREQ[1:9]#
ITP_SEL
FCTSEL1
SEL_CLKREQ
48M
VDD48
I2C
Logic
SDATA
SCLK
27MNon-spread
VDD48
Dvider
27M
PLL
27MSpread
VDD48
DOT96T
DOT96C
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