參數(shù)資料
型號(hào): CY28445LFXC-5
廠商: Silicon Laboratories Inc
文件頁數(shù): 6/25頁
文件大小: 0K
描述: IC CLOCK CALISTOGA CK410M 68QFN
標(biāo)準(zhǔn)包裝: 260
類型: 時(shí)鐘/頻率發(fā)生器
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: LVTTL,晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 3:22
差分 - 輸入:輸出: 無/是
頻率 - 最大: 200MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 68-QFN(8x8)
包裝: 托盤
CY28445-5
..................... Document #: 38-07739 Rev *C Page 14 of 25
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs .............................................. Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
CLKREQ# Description
The CLKREQ# signals are active LOW inputs used for clean
enabling and disabling selected SRC outputs. The outputs
controlled by CLKREQ# are determined by the settings in
register byte 8. The CLKREQ# signal is a de-bounced signal
in that it’s state must remain unchanged during two consec-
utive rising edges of SRCC to be recognized as a valid
assertion or deassertion. (The assertion and deassertion of
this signal is absolutely asynchronous.).
Figure 1. Crystal Capacitive Clarification
XTAL
Ce2
Ce1
Cs1
Cs2
X1
X2
Ci1
Ci2
Clock Chip
Trace
2.8 pF
Trim
33 pF
Pin
3 to 6p
Figure 2. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
()
1
=
CLe
Figure 3. CLK_REQ# Deassertion/Assertion Waveform
SRCT(stoppable)
SRCC(free running)
SRCT(free running)
CLKREQ#X
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