參數(shù)資料
型號(hào)： CY28410ZXC
廠(chǎng)商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： XO, clock
英文描述： Paired Cable; Number of Conductors:24; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyvinylchloride (PVC); Number of Pairs:12; Conductor Material:Copper; Features:Traditional Analog Audio Applications RoHS Compliant: Yes
中文描述： 266 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 6 X 12 MM, LEAD FREE, MO-153, TSSOP2-56
文件頁(yè)數(shù)： 7/18頁(yè)
文件大?。?/td> 281K
代理商： CY28410ZXC
CY28410
Document #: 38-07593 Rev. *C
Page 7 of 18
Crystal Recommendations
The CY28410 requires a Parallel Resonance Crystal.
Substi-
tuting a series resonance crystal will cause the CY28410 to
operate at the wrong frequency and \violate the ppm specifi-
cation. For most applications there is a 300ppm frequency shift
between series and parallel crystals due to incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
The following diagram shows a typical crystal configuration
using the two trim capacitors. An important clarification for the
following discussion is that the trim capacitors are in series
with the crystal not parallel. It’s a common misconception that
load capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
2
Externally
selected
Externally
selected
Externally
selected
CPUT/C
FS_C. Reflects the value of the FS_C pin sampled on power-up
0 = FS_C was low during VTT_PWRGD# assertion
FS_B. Reflects the value of the FS_B pin sampled on power-up
0 = FS_B was low during VTT_PWRGD# assertion
FS_A. Reflects the value of the FS_A pin sampled on power-up
0 = FS_A was low during VTT_PWRGD# assertion
1
CPUT/C
0
CPUT/C
Byte 7: Vendor ID
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
1
0
1
0
0
0
Name
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Byte 6: Control Register 6
(continued)
Bit
@Pup
Name
Description
Table 5. Crystal Recommendations
Frequency
(Fund)
14.31818 MHz
Cut
Loading
Load Cap
Drive
(max.)
0.1 mW
Shunt Cap
(max.)
5 pF
Motional
(max.)
0.016 pF
Tolerance
(max.)
35 ppm
Stability
(max.)
30 ppm
Aging
(max.)
5 ppm
AT
Parallel
20 pF
相關(guān)PDF資料
PDF描述
CY28410OC Hook-Up Wire; Conductor Size AWG:22; No. Strands x Strand Size:7 x 30; Jacket Color:Gray; Approval Bodies:UL; Approval Categories:UL AWM Style 1213; Passes VW-1 Flame Test; Cable/Wire MIL SPEC:MIL-W-16878/4 Type E RoHS Compliant: Yes
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY28410ZXC-2 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Clock Generator for Intel Grantsdale Chipset
CY28410ZXC-2T 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Clock Generator for Intel Grantsdale Chipset
CY28410ZXCT 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 SysClk Intel Lakeprt & Grantsdale Chipset RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
CY28411 制造商:SPECTRALINEAR 制造商全稱(chēng):SPECTRALINEAR 功能描述:Clock Generator for Intel Alviso Chipset
CY28411-1 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Clock Generator for Intel Alviso Chipset
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