參數(shù)資料
型號(hào): CY28410OXC-2
廠商: Silicon Laboratories Inc
文件頁數(shù): 3/16頁
文件大小: 0K
描述: IC CLOCK CK410 GRANTSDALE 56SSOP
標(biāo)準(zhǔn)包裝: 26
類型: 時(shí)鐘/頻率發(fā)生器
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: 晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:21
差分 - 輸入:輸出: 無/是
頻率 - 最大: 266MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 56-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 56-SSOP
包裝: 管件
CY28410-2
...................... Document #: 38-07747 Rev *.* Page 11 of 16
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing
is NOT required.
DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
VDD_A,
VDD_REF,
VDD_PCI,
VDD_3V66,
VDD_48,
VDD_CPU
3.3V Operating Voltage
3.3 ± 5%
3.135
3.465
V
VILI2C
Input Low Voltage
SDATA, SCLK
1.0
V
VIHI2C
Input High Voltage
SDATA, SCLK
2.2
V
VIL_FS
FS_A/FS_B Input Low Voltage
VSS – 0.3
0.35
V
VIH_FS
FS_A/FS_B Input High Voltage
0.7
VDD + 0.5
V
VILFS_C
FS_C Low Range
0
0.35
V
VIMFS_C
FS_C Mid Range
0.7
1.7
V
VIH FS_C
FS_C High Range
2.1
VDD
V
VIL
Input Low Voltage
VSS – 0.5
0.8
V
VIH
Input High Voltage
2.0
VDD + 0.5
V
IIL
Input Low Leakage Current
except internal pull-up resistors, 0 < VIN < VDD
–5
A
IIH
Input High Leakage Current
except internal pull-down resistors, 0 < VIN < VDD
5
A
VOL
Output Low Voltage
IOL = 1 mA
0.4
V
VOH
Output High Voltage
IOH = –1 mA
2.4
V
IOZ
High-impedance Output Current
–10
10
A
CIN
Input Pin Capacitance
2
5
pF
COUT
Output Pin Capacitance
3
6
pF
LIN
Pin Inductance
–7
nH
VXIH
Xin High Voltage
0.7VDD
VDD
V
VXIL
Xin Low Voltage
00.3VDD
V
IDD3.3V
Dynamic Supply Current
At max load and freq per Figure 7
–550
mA
IPD3.3V
Power-down Supply Current
PD asserted, Outputs driven
70
mA
IPD3.3V
Power-down Supply Current
PD asserted, Outputs Hi-Z
2
mA
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
Crystal
TDC
XIN Duty Cycle
The device will operate reliably with input
duty cycles up to 30/70 but the REF clock
duty cycle will not be within specification
47.5
52.5
%
TPERIOD
XIN Period
When XIN is driven from an external clock
source
69.841
71.0
ns
TR / TF
XIN Rise and Fall Times
Measured between 0.3VDD and 0.7VDD
–10.0
ns
TCCJ
XIN Cycle to Cycle Jitter
As an average over 1-
s duration
500
ps
LACC
Long-term Accuracy
Over 150 ms
300
ppm
CPU at 0.7V
TDC
CPUT and CPUC Duty Cycle
Measured at crossing point VOX
43
57
%
TPERIOD
100-MHz CPUT and CPUC Period
Measured at crossing point VOX
9.997001 10.00300
ns
Absolute Maximum Conditions
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