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參數(shù)資料
型號(hào)： CY28409OXCT
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 6/16頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK CK409GRANTSDALE 56TSSOP
標(biāo)準(zhǔn)包裝： 1,000
類型： *
PLL： 是
輸入： 晶體
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 1:21
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 400MHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 70°C
安裝類型： *
封裝/外殼： *
供應(yīng)商設(shè)備封裝： *
包裝： *
其它名稱： SLCY28409OXCT
CY28409
......................Document #: 38-07445 Rev. *D Page 14 of 16
TR / TF
PCIF and PCI rise and fall times
Measured between 0.8V and 2.0V
0.5
2.0
ns
TSKEW
Any PCI clock to Any PCI clock Skew Measurement at 1.5V
–
500
ps
TCCJ
PCIF and PCI Cycle to Cycle Jitter
Measurement at 1.5V
–
250
ps
DOT
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Period
Measurement at 1.5V
20.8271
20.8396
ns
TSKEW
Any 48-MHz to 48-MHz Clock Skew
Measured at crossing point VOX
–
500
ps
THIGH
USB high time
Measurement at 2.0V
8.994
10.486
ns
TLOW
USB low time
Measurement at 0.8V
8.794
10.386
ns
TR / TF
Rise and Fall Times
Measured between 0.8V and 2.0V
0.5
1.0
ns
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
–
350
ps
USB
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Period
Measurement at 1.5V
20.8271
20.8396
ns
TSKEW
Any 48-MHz to 48-MHz Clock Skew
Measured at crossing point VOX
–
500
ps
THIGH
USB high time
Measurement at 2.0V
8.094
10.036
ns
TLOW
USB low time
Measurement at 0.8V
7.694
9.836
ns
TR / TF
Rise and Fall Times
Measured between 0.8V and 2.0V
1.0
2.0
ns
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
–
350
ps
REF
TDC
REF Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
REF Period
Measurement at 1.5V
69.827
69.855
ns
TSKEW
Any REF to REF Clock Skew
Measured at crossing point VOX
–
500
ps
TR / TF
REF Rise and Fall Times
Measured between 0.8V and 2.0V
0.5
2.0
ns
TCCJ
REF Cycle to Cycle Jitter
Measurement at 1.5V
–
1000
ps
ENABLE/DISABLE and SET-UP
TSTABLE
Clock Stabilization from Power-up
–
1.8
ms
TSS
Stopclock Set-up Time
10.0
–
ns
TSH
Stopclock Hold Time
0
–
ns
AC Electrical Specifications (continued)
Parameter
Description
Condition
Min.
Max.
Unit
Table 7. Group Timing Relationship and Tolerances
Group
Conditions
Offset
Min.
Max.
3V66 to PCI
3V66 Leads PCI
1.5 ns
3.5 ns
Table 8. USB to DOT Phase Offset
Parameter
Typical
Value
Tolerance
DOT Skew
0°
0.0 ns
1000 ps
USB Skew
180°
0.0 ns
1000 ps
VCH SKew
0°
0.0 ns
1000 ps
Table 9. Maximum Lumped Capacitive Output Loads
Clock
Max Load
Unit
PCI Clocks
30
pF
3V66 Clocks
30
pF
USB Clock
20
pF
DOT Clock
10
pF
REF Clock
30
pF
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