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參數(shù)資料
| 型號： | CY28401OC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 100-MHz Differential Buffer for PCI Express and SATA |
| 中文描述： | 28401 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 235K |
| 代理商： | CY28401OC |
CY28401
Document #: 38-07592 Rev. **
Page 2 of 14
Serial Data Interface
To enhance the flexibility and function of the clock buffer, a
two-signal serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock
output buffers, can be individually enabled or disabled. The
registers associated with the Serial Data Interface initializes to
their default setting upon power-up, and therefore use of this
interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface cannot be used during system operation for
power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 1
.
The block write and block read protocol is outlined in
Table 2
while
Table 3
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11011100 (DCh).
Pin Description
Pin
Name
Type
I,DIF
O,DIF
Description
4,5
8,9,12,13,16,17,20,21,29,30,
33,34,37,38,41,42
6,7,14,15,35,36,43,44
SRCT_IN, SRCC_IN
DIFT/C(7:0)
0.7V Differential SRC inputs from the clock synthesizer
0.7V Differential Clock Outputs
OE_(7:0)
I,SE
3.3V LVTTL active low input for three-stating differential
outputs
3.3V LVTTL input for selecting PLL bandwidth
3.3V LVTTL output, transitions high when PL lock is
achieved (latched output)
3.3V LVTTL input for Power Down, active low
3.3V LVTTL input for selecting input frequency divided by
two, active low
3.3V LVTTL input for SRC_Stop#, active low
SMBus Slave Clock Input
I/O,OC
Open collector SMBus data
I
A precision resistor is attached to this pin to set the differ-
ential output current
I
3.3V LVTTL input for selecting fan-out or PLL operation
3.3V
3.3V Power Supply for PLL
GND
Ground for PLL
I
Ground for outputs
I
3.3V power supply for outputs
28
45
HIGH_BW#
LOCK
I,SE
O,SE
26
1
PWRDWN#
SRC_DIV/2#
I,SE
I,SE
27
23
24
46
SRC_STOP#
SCLK
SDATA
IREF
I,SE
I,SE
22
48
47
3,10,18,25,32,40
2,11,19,31,39
PLL/BYPASS#
VDD_A
VSS_A
VSS
VDD
Table 1. Command Code Definition
Bit
7
Description
0 = Block read or block write operation
1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
(6:0)
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
1
2:8
9
10
Description
Bit
1
2:8
9
10
Description
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
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PDF描述 |
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| CY28401OCT | 100-MHz Differential Buffer for PCI Express and SATA |
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| CY28405OXCT | CK409-Compliant Clock Synthesizer |
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| CY28405OCT | Circular Connector; No. of Contacts:6; Series:; Body Material:Aluminum; Connecting Termination:Solder; Connector Shell Size:10; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:10-6 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY28401OCT | 功能描述:時鐘緩沖器 100 MHz Diff Buffer PCIe & SATA 1in 4out RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28401OXC | 功能描述:時鐘緩沖器 100 MHz Diff Buffer PCIe & SATA 1in 4out RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28401OXCT | 功能描述:時鐘緩沖器 100 MHz Diff Buffer PCIe & SATA 1in 4out RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28404 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:CK409-Compliant Clock Synthesizer |
| CY28404OC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CK409-COMPLIANT CLOCK SYNTHESIZER |
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