參數(shù)資料
型號: CY28378OXC
廠商: Silicon Laboratories Inc
文件頁數(shù): 4/21頁
文件大小: 0K
描述: IC CLOCK CK408/TITAN 845 48SSOP
標(biāo)準(zhǔn)包裝: 30
類型: 時鐘/頻率發(fā)生器
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: 晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:21
差分 - 輸入:輸出: 無/是
頻率 - 最大: 203MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 48-SSOP
包裝: 管件
CY28378
...................... Document #: 38-07519 Rev. ** Page 12 of 21
PD# (Power-down) Clarification
The PD# (Power Down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is low, all clocks are driven to a LOW value and held there and
the VCO and PLLs are also powered down. All clocks are shut
down in a synchronous manner so has not to cause glitches
while transitioning to the low “stopped” state.
PD# – Assertion
Table 7. Maximum Lumped Capacitive Output Loads
Clock
Max Load
Units
PCI, PCI_F
20
pF
3V66
30
pF
48M_24MHz, 48MHz
20
pF
REF
30
pF
CPUT/C
CPU_ITP
pF
Table 8. Group Timing Relationship and Tolerances
Offset
Tolerance
(or Range)
Conditions
Notes
3V66 to PCI
Typical 2.5 ns
1.5 – 3.5 ns
3V66 leads
See Note 2
PWRDWN#
AGP, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.131818
CPUC, 133MHz
CPUT, 133MHz
Figure 2. Power-down Assertion Timing Waveforms
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