參數(shù)資料
型號: CY28378OCT
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: FTG for Pentium 4 and Intel 845 Series Chipset
中文描述: 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: SSOP-48
文件頁數(shù): 12/22頁
文件大?。?/td> 174K
代理商: CY28378OCT
CY28378
Document #: 38-07519 Rev. **
Page 12 of 22
Table 7. Maximum Lumped Capacitive Output Loads
PD# (Power-down) Clarification
The PD# (Power Down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is low, all clocks are driven to a LOW value and held there and
the VCO and PLLs are also powered down. All clocks are shut
down in a synchronous manner so has not to cause glitches
while transitioning to the low “stopped” state.
PD# – Assertion
Clock
Max Load
20
30
20
30
See
Figure 4
Units
pF
pF
pF
pF
pF
PCI, PCI_F
3V66
48M_24MHz, 48MHz
REF
CPUT/C
CPU_ITP
Table 8. Group Timing Relationship and Tolerances
Offset
Tolerance
(or Range)
1.5 – 3.5 ns
Conditions
3V66 leads
Notes
See
Note 2
3V66 to PCI
Typical 2.5 ns
PWRDWN#
AGP, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.131818
CPUC, 133MHz
CPUT, 133MHz
Figure 2. Power-down Assertion Timing Waveforms
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