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參數(shù)資料
| 型號： | CY28354OXC-400T |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFF 273MHZ 4DDR DIMM 48SSOP |
| 標準包裝： | 1,000 |
| 類型： | 扇出緩沖器（分配） |
| PLL： | 無 |
| 主要目的： | 存儲器，DDR |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 2 |
| 比率 - 輸入:輸出： | 1:12 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 400MHz |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應商設備封裝： | * |
| 包裝： | * |
CY28354-400
.......................... Document #: 38-07615 Rev. *B Page 5 of 8
Absolute Maximum Conditions[1]
Parameter
Description
Min.
Max.
Unit
VDD
Supply Voltage to Ground Potential
–0.5
4.6
V
Vin
DC Input Voltage (except BUFF_IN)
–0.3
VDD+0.3
V
Vout
Output Voltage
1.1
VDD–0.4
V
Ts
Temperature, Storage
–65
+150
°C
Ta
Temperature, Operating Ambient
0
85
°C
JC
Dissipation, Junction to Case (Mil-Spec 883E Method 1012.1)
36.39
°C/W
JA
Dissipation, Junction to Ambient (JEDEC (JESD 51)
77.99
°C/W
ESDh
ESD Protection (Human Body Model)
–
2000
V
DC Electrical Specifications
Parameter
Description
Min.
Typ.
Max.
Unit
VDD2.5
Supply Voltage
2.3
–
2.7
V
COUT
Output Capacitance
–
6
–
pF
CIN
Input Capacitance
–
5
–
pF
AC Electrical Specifications
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
VIL
Input LOW Voltage
For all pins except SMBus
0.3
–
0.7
V
VIH
Input HIGH Voltage
1.7
–
VDD + 0.3
V
IOH
Output HIGH Current
VDD = 2.375V, VOUT = 1V
–
–12
mA
IOL
Output LOW Current
VDD = 2.375V, VOUT = 1.2V
–
12
mA
VOL
Output LOW Voltage[2]
IOL = 12 mA, VDD = 2.375V
–
0.5
V
VOH
Output HIGH Voltage[2]
IOH = –12 mA, VDD = 2.375V
1.7
–
V
IDD
Supply Current[2]
Unloaded outputs, 133 MHz
–
400
mA
IDD
Supply Current
Loaded outputs, 133 MHz
–
500
mA
IDDPD
Supply Current
All outputs off
–
2
mA
VOUT
Output Voltage Swing
See Test Circuity. See Figure 1
0.7
–
VDD + 0.6
V
VOC
Output Crossing Voltage
VDD/2–0.3
VDD/2
VDD/2+0.3
V
INDC
Input Clock Duty Cycle
40
–
60
%
Switching Characteristics[3]
Parameter
Name
Test Conditions
Min.
Typ.
Max.
Unit
–
Operating Frequency
60
210
MHz
–
Measured differentially at VCROSS
INDC –2%
–
INDC +2%
%
t3d
DDR Rising Edge Rate[2]
Measured single ended at 20% to 80% of VDIF
1.0
2.0
5.0
V/ns
t4d
DDR Falling Edge Rate[2]
Measured single ended at 80% to 20% of VDIF
1.0
2.0
5.0
V/ns
t5
Output to Output Skew for
DDR[2]
All outputs equally loaded.
See Figure 1.
––
75
ps
t6
Input to Output Propagation
delay
At output load of 15 pFn
–
6
ns
Notes:
1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3. All parameters specified with loaded outputs.
4. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.
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