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參數(shù)資料
| 型號： | CY28353OXC-2 |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIFF/DRIVER PLL 28TSSOP |
| 標準包裝： | 47 |
| 類型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 頻率 - 最大： | 170MHz |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應商設備封裝： | * |
| 包裝： | * |
CY28353-2
.......................... Document #: 38-07372 Rev. *B Page 6 of 9
AC Parameters VDD = VDDQ = 2.5V ± 5%, TA = 0°C to +70°C
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
fCLK
Operating Clock Frequency
AVDD, VDD = 2.5V ± 0.2V
60
170
MHz
tDC
Input Clock Duty Cycle
40
60
%
tlock
Maximum PLL lock Time
100
s
Tr / Tf
Output Clocks Slew Rate
20% to 80% of VOD
1
2.5
V/ns
tpZL, tpZH
Output Enable Time[12](all outputs)
3
ns
tpLZ, tpHZ
Output Disable Time[12] (all outputs)
ns
tCCJ
Cycle to Cycle Jitter
f > 66 MHz
–100
100
ps
tjit(h-per)
Half-period jitter[14]
f > 66 MHz
–100
100
ps
tPLH
Low-to-High Propagation Delay,
CLKINT to CLKT[0:5]
1.5
3.5
6
ns
tPHL
High-to-Low Propagation Delay,
CLKINT to CLKT[0:5]
1.5
3.5
6
ns
tSKEW
Any Output to Any Output Skew[13]
100
ps
tPHASE
Phase Error[13]
–150
150
ps
tPHASEJ
Phase Error Jitter
f > 66MHz
–50
50
ps
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply srquencing is NOT required.
4. Unused inputs must be held HIGH or LOW to prevent them from floating.
5. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the comple-
mentary input level.
6. Differential cross-point input voltage is expected to track VDDQ and is the voltage at which the differential signals must be crossing.
7. For load conditions see Figure 7.
8. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120
resistor. See Figure 7.
9. All outputs switching loaded with 16 pF in 60
environment. See Figure 7.
10. Parameters are guaranteed by design and characterization. Not 100% tested in production.
11. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a down
spread of –0.5%.
12. Refers to transition of non-inverting output.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28353OXC-2T | 功能描述:時鐘緩沖器 Differential clock Buffer/Driver RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28354-400 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:210-MHz 24-Output Buffer for 4-DDR DIMMS for VIA Chipsets Support |
| CY28354OXC-400 | 功能描述:時鐘緩沖器 273MHz Output Buffer for 4 DDR DIMMs RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28354OXC-400T | 功能描述:時鐘緩沖器 273MHz Output Buffer for 4 DDR DIMMs RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28358 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:200-MHz Differential Clock Buffer/Driver |
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