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參數(shù)資料
| 型號(hào)： | CY28341OCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| 中文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | SSOP-56 |
| 文件頁數(shù)： | 4/21頁 |
| 文件大?。?/td> | 189K |
| 代理商： | CY28341OCT |
CY28341
Document #: 38-07367 Rev. *A
Page 4 of 21
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers, etc., can be individually enabled or
disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read,
Block Write, and Block Read operation from the controller. For
Block Write/Read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For Byte Write and Byte Read operations,
the system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 2
.
The Block Write and Block Read protocol is outlined in
Table 3
,
while
Table 4
outlines the corresponding Byte Write and Byte
Read protocol. The slave receiver address is 11010010 (D2h).
Table 2. Command Code Definition
Bit
7
Description
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits
should be
“
0000000
”
Table 3. Block Read and Block Write Protocol
(6:0)
Block Write Protocol
Description
Block Read Protocol
Bit
1
2:8
9
10
11:18
Bit
1
2:8
9
10
11:18
Description
Start
Start
Slave address
–
7 bits
Write
Acknowledge from slave
Command Code
–
8-bit
“
00000000
”
stands for
Block operation
Acknowledge from slave
Repeat start
Slave address
–
7 bits
Read
Acknowledge from slave
Byte count from slave
–
8 bits
Acknowledge
Data byte from slave
–
8 bits
Acknowledge
Data byte from slave
–
8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data byte N from slave
–
8 bits
Not Acknowledge
Stop
Slave address
–
7 bits
Write
Acknowledge from slave
Command Code
–
8-bit
“
00000000
”
stands for
Block operation
Acknowledge from slave
Byte Count
–
8 bits
Acknowledge from slave
Data byte 0
–
8 bits
Acknowledge from slave
Data byte 1
–
8 bits
Acknowledge from slave
Data Byte N/Slave acknowledge...
Data Byte N
–
8 bits
Acknowledge from slave
Stop
19
19
20
20:27
28
29:36
37
38:45
46
....
....
....
....
21:27
28
29
30:37
38
39:46
47
48:55
56
....
....
....
....
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PDF描述 |
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| CY28341OC | Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems |
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| CY28346OC | CONN BNC PLUG CRIMP RG-TFE-59,62 |
| CY28346OCT | CONN BNC PLUG CRIMP RG-59,62 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28341OXC-2 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
| CY28341OXC-2T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
| CY28341ZC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28341ZC-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
| CY28341ZC-2T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
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