參數(shù)資料
型號: CY28329
廠商: Cypress Semiconductor Corp.
英文描述: 133-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs
中文描述: 133 - MHz的擴頻時鐘合成器/驅(qū)動器,差分輸出的CPU
文件頁數(shù): 5/17頁
文件大?。?/td> 290K
代理商: CY28329
CY28329
Document #: 38-07040 Rev. *E
Page 5 of 17
Data Byte 1:
Bit
Pin#
53, 54
Name
Description
Type
R
R/W
Power On
Default
HW
1
Bit 7
Bit 6
CPU Mult0 Value
CPU3 Output Enable
1 = Enabled; 0 = Disabled
Reserved, set = 0
Reserved, set = 0
Reserved, set = 0
CPU2 Output Enable
1 = Enabled; 0 = Disabled
CPU1Output Enable
1 = Enabled; 0= Disabled
CPU0 Output Enable
1 = Enabled; 0 = Disabled
CPU3
CPU3#
CPU2
CPU2#
CPU1
CPU1#
CPU0
CPU0#
Bit 5
Bit 4
Bit 3
Bit 2
R/W
R/W
R/W
R/W
0
0
0
1
44, 45
Bit 1
48, 49
R/W
1
Bit 0
51, 52
R/W
1
Data Byte 2:
Bit
Pin#
18
Name
PCI6
Pin Description
Type
R
R/W
Power On
Default
0
1
Bit 7
Bit 6
Reserved, set = 0
PCI6 Output Enable
1 = Enabled; 0 = Disabled
PCI5 Output Enable
1 = Enabled; 0 = Disabled
PCI4 Output Enable
1 = Enabled; 0 = Disabled
PCI3 Output Enable
1 = Enabled; 0 = Disabled
PCI2 Output Enable
1 = Enabled; 0 = Disabled
PCI1 Output Enable
1 = Enabled; 0 = Disabled
PCI0 Output Enable
1 = Enabled; 0 = Disabled
Bit 5
17
PCI5
R/W
1
Bit 4
16
PCI4
R/W
1
Bit 3
13
PCI3
R/W
1
Bit 2
12
PCI2
R/W
1
Bit 1
11
PCI1
R/W
1
Bit 0
10
PCI0
R/W
1
Data Byte 3:
Bit
Pin#
38
39
7
Name
DOT
USB
PCI_F2
Pin Description
Type
R/W
R/W
R/W
Power On
Default
1
1
0
Bit 7
Bit 6
Bit 5
DOT 48 MHz Output Enable, 1 = enabled, 0 = disabled
USB 48 MHz Output Enable, 1 = enabled, 0 = disabled
Allow control of PCI_F2 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
Allow control of PCI_F1 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
Allow control of PCI_F0 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
PCI_F2 Output Enable, 1 = enabled, 0 = disabled
PCI_F1Output Enable, 1 = enabled, 0 = disabled
PCI_F0 Output Enable, 1 = enabled, 0 = disabled
Bit 4
6
PCI_F1
R/W
0
Bit 3
5
PCI_F0
R/W
0
Bit 2
Bit 1
Bit 0
7
6
5
PCI_F2
PCI_F1
PCI_F0
R/W
R/W
R/W
1
1
1
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