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參數(shù)資料
| 型號： | CY28158OXCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Spread Spectrum Timing Solution for Serverworks Chipset |
| 中文描述： | 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | LEAD FREE, SSOP-56 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 220K |
| 代理商： | CY28158OXCT |
Spread Spectrum Timing Solution for Serverworks Chipset
CY28158
Cypress Semiconductor Corporation
Document #: 38-07039 Rev. *B
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised June 25, 2004
Features
Maximized EMI suppression using Cypress’s spread
spectrum technology
Based on Industry Standard CK133 Pinout with all out-
puts compliant to CK98 specifications
0.5% downspread outputs deliver up to 10dB lower EMI
6 skew-controlled copies of CPU output
6 copies of PCI output (synchronous w/CPU output)
2 copies of 66 MHz fixed frequency 3.3V clock
3 copies of 16.67 MHz IOAPIC clock, synchronous to
CPU clock
1 copy of 48 MHz USB output
2 copies of 14.31818 MHz reference clock
Programmable to 133 or 100 MHz operation
Power management control pins for clock stop and
shut down
Available in 56-pin SSOP
Key Specifications
Supply Voltages:......................................V
DD33
= 3.3V ± 5%
................................................................V
DD25
= 2.5V ± 5%
CPU Output Jitter: ....................................................<150 ps
CPU Output Skew: ....................................................<175 ps
CPU to 3V66 Output Offset: 0.0 to1.5 ns (CPU leads)
CPU to IOAPIC Output Offset 1.5 to 4.0 ns (CPU leads)
CPU to PCI Output Offset................. 0 to 4.0 ns (CPU leads)
Table 1. Pin Selectable Frequency.
SEL133/100#
1
0
CPU0:5 (MHz)
133
100
PCI
33.3
33.3
Block Diagram
Pin Configuration
GND_REF
REF0
REF1
VDD_REF
X1
X2
GND_PCI
GND_PCI
PCI_F
VDD_PCI
PCI1
PCI2
GND_PCI
PCI3
PCI4
VDD_PCI
VDD_PCI
PCI5
GND_PCI
GND_3V66
GND_3V66
VDD_3V66
VDD_3V66
GND_3V66
3V66_0
3V66_1
VDD_3V66
SEL133/100#
C
VDD_IOAPIC
IOAPIC2
IOAPIC1
IOAPIC0
GND_IOAPIC
VDD_CPU
CPU5
CPU4
GND_CPU
VDD_CPU
CPU3
CPU2
GND_CPU
VDD_CPU
CPU1
CPU0
GND_CPU
VDDA
GNDA
PCI_STOP#
CPU_STOP#
PWR_DWN#
SPREAD#
SEL1
SEL0
VDD_48MHZ
48MHZ
GND_48MHZ
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
REF0:1
CPU0:5
3V66_0:1
XTAL
OSC
PLL 1
SPREAD#
SEL0
SEL1
SEL133/100#
X2
X1
PCI_F
PCI1:5
IOAPIC0:2
PLL2
STOP
Clock
Logic
Power
Down
Logic
Tristate
Logic
CPU_STOP#
÷2/÷1.5
STOP
Clock
Logic
÷2
STOP
Clock
Logic
÷2
2
6
2
1
5
3
1
PCI_STOP#
PWRDWN#
48MHz
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| CY28158PVC | Spread Spectrum Timing Solution for Serverworks Chipset |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28158PVC | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Spread Spectrum Timing Solution for Serverworks Chipset |
| CY28158PVCT | 制造商:Cypress Semiconductor 功能描述: |
| CY28159 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Serverworks Grand Champion Chipset Applications |
| CY28159PVC | 制造商:Rochester Electronics LLC 功能描述:FTG FOR SERVERWORKS GRAND CHAMPION CHIPSET - Bulk |
| CY28159PVCT | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Serverworks Grand Champion Chipset Applications |
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