參數(shù)資料
型號: CY27C256-150WC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 32K x 8-Bit CMOS EPROM
中文描述: 32K X 8 UVPROM, 150 ns, CDIP28
封裝: 0.600 INCH, WINDOWED, CERDIP-28
文件頁數(shù): 1/11頁
文件大?。?/td> 260K
代理商: CY27C256-150WC
32K x 8-Bit CMOS EPROM
fax id: 3013
CY27C256
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
May 1993 – Revised August 1994
408-943-2600
1CY27C256
Features
Wide speed range
—45 ns to 200 ns (commercial and military)
Low power
—248 mW (commercial)
—303 mW (military)
Low standby power
—Less than 83 mW when deselected
±
10% Power supply tolerance
Functional Description
The CY27C256 is a high-performance 32,768-word by 8-bit
CMOS EPROM. When disabled (CE HIGH), the CY27C256
automatically powers down into a low-power stand-by mode.
The CY27C256 is packaged in the industry standard 600-mil
DIP, PLCC, and TSOP packages. The CY27C256 is also avail-
able in a CerDIP package equipped with an erasure window
to provide for reprogrammability. When exposed to UV light,
the EPROM is erased and can be reprogrammed. The mem-
ory cells utilize proven EPROM floating gate technology and
byte-wide intelligent programming algorithms.
The CY27C256 offers the advantage of lower power and su-
perior performance and programming yield. The EPROM cell
requires only 12.5V for the super voltage, and low current re-
quirements allow for gang programming. The EPROM cells
allow each memory location to be tested 100% because each
location is written into, erased, and repeatedly exercised prior
to encapsulation. Each EPROM is also tested for AC perfor-
mance to guarantee that after customer programming, the
product will meet both DC and AC specification limits.
Reading the CY27C256 is accomplished by placing active
LOW signals on OE and CE. The contents of the memory location
addressed by the address lines (A
0
- A
14
) will become available on
the output lines (O
0
- O
7
).
Note:
1.
For PLCC only: Pins 1 and 17 are common and tied to the die attach pad. They must therefore be DU (don’t use) for the PLCC package.
Logic Block Diagram
Pin Configurations
27c256–1
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
POWER–DOWN
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
CE
P256 x 1024
ARRAY
8 x 1 OF 128
A
13
A
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
17
18
19
20
24
23
22
21
25
28
27
26
12
13
31
4
5
6
7
8
9
10
11
3 2 1
30
14151617
26
25
24
23
22
21
181920
27
28
29
32
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
V
CC
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
O
7
O
6
O
5
O
4
O
3
27c256–2
27c256–3
A
9
A
11
NC
OE
A
10
CE
O
7
O
6
A
8
V
PP
27C256
NC
O
0
A
5
A
4
A
3
A
2
A
1
A
0
A
6
DIP/Flatpack
27C256
AROW
LCC/PLCC
[1]
OE
COLUMN
ADDRESS
相關(guān)PDF資料
PDF描述
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