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參數(shù)資料
| 型號： | CY26112 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | One-PLL General Purpose Clock Generator |
| 中文描述： | 一個通用鎖相環(huán)時鐘發(fā)生器 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大小： | 124K |
| 代理商： | CY26112 |
CY26112
Document #: 38-07096 Rev. OBS
Page 3 of 5
DC Electrical Characteristics
AC Electrical Characteristics
Parameter
[1]
DC
Parameter
[1]
I
OH
I
OL
I
OH
I
OL
V
IH
V
IL
C
IN
I
IZ
I
VDD
I
VDDL
I
VDDL
Name
Description
Min.
12
12
8
8
0.7
Typ.
24
24
16
16
Max.
Unit
mA
mA
mA
mA
V
DD
V
DD
pF
μ
A
mA
mA
mA
Output High Current
Output Low Current
Output High Current
Output Low Current
Input High Voltage
Input Low Voltage
Input Capacitance
Input Leakage Current
Supply Current
Supply Current
Supply Current
V
OH
= V
DD
D 0.5, V
DD
/V
DDL
= 3.3V
V
OL
= 0.5, V
DD
/V
DDL
= 3.3V
V
OH
= V
DDL
D 0.5, V
DDL
= 2.5V
V
OL
= 0.5, V
DDL
= 2.5V
CMOS levels, 70% of V
DD
CMOS levels, 30% of V
DD
OE and FS Pins
OE and FS Pins
AV
DD
/V
DD
Current
V
DDL
Current (V
DDL
= 3.6V)
V
DDL
Current (V
DDL
= 2.625V)
0.3
7
5
25
7
5
Name
Description
Min.
45
Typ.
50
Max.
55
Unit
%
Duty Cycle is defined in Figure 2; t1/t2 @ 50%
of V
DD
t
3
Rising Edge Slew Rate Output Clock Rise Time, 20% D 80% of
V
DD
/V
DDL
=3.3V
Rising Edge Slew Rate Output Clock Rise Time, 20% D 80% of
V
DDL
= 2.5V
Falling Edge Slew
Rate
V
DD
/V
DDL
=3.3V
Falling Edge Slew
Rate
V
DDL
= 2.5V
Skew
Delay between related outputs at rising edge
Clock Jitter
Peak to Peak period jitter
PLL Lock Time
0.8
1.4
V/ns
t
3
0.6
1.2
V/ns
t
4
Output Clock Fall Time, 80% D 20% of
0.8
1.4
V/ns
t
4
Output Clock Fall Time, 80% D 20% of
0.6
1.2
V/ns
t
5
t
9
t
10
250
350
3
ps
ms
Figure 1. Duty Cycle Definition; DC = t2/t2\.
Figure 2. Rise and Fall Time Definitions.
Note:
2.
Not 100% tested.
t1
t2
CLK
50%
50%
t3
CLK
80%
20%
t4
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PDF描述 |
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| CY26112ZC | One-PLL General Purpose Clock Generator |
| CY27C128-200WC | 128K (16K x 8-Bit) CMOS EPROM |
| CY27C128-70WMB | 128K (16K x 8-Bit) CMOS EPROM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY26112ZC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:One-PLL General Purpose Clock Generator |
| CY26113 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| CY26113ZC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MISCELLANEOUS CLOCK GENERATOR|CMOS|TSSOP|16PIN|PLASTIC |
| CY26114 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:One-PLL Clock Generator |
| CY26114KZC | 功能描述:鎖相環(huán) - PLL One-PLL Clock Gen RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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