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參數(shù)資料
| 型號： | CY26111ZC |
| 英文描述： | MISCELLANEOUS CLOCK GENERATOR|CMOS|TSSOP|16PIN|PLASTIC |
| 中文描述： | 雜項時鐘發(fā)生器|的CMOS | TSSOP封裝| 16PIN |塑料 |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 50K |
| 代理商： | CY26111ZC |
CY26111
Document #: 38-07095 Rev. *A
Page 3 of 5
DC Electrical Characteristics
AC Electrical Characteristics
Parame-
ter
[1]
I
OH
I
OL
I
OH
I
OL
V
IH
V
IL
C
IN
I
IZ
I
VDD
I
VDDL
I
VDDL
Name
Description
Min.
12
12
8
8
0.7
Typ.
24
24
16
16
Max.
Unit
mA
mA
mA
mA
V
DD
V
DD
pF
μ
A
mA
mA
mA
Output High Current
Output Low Current
Output High Current
Output Low Current
Input High Voltage
Input Low Voltage
Input Capacitance
Input Leakage Current
Supply Current
Supply Current
Supply Current
V
OH
= V
DD
–
0.5, V
DD
/V
DDL
= 3.3V
V
OL
= 0.5, V
DD
/V
DDL
= 3.3V
V
OH
= V
DDL
–
0.5, V
DDL
= 2.5V
V
OL
= 0.5, V
DDL
= 2.5V
CMOS levels, 70% of V
DD
CMOS levels, 30% of V
DD
OE Pin
OE Pin
AV
DD
/V
DD
Current
V
DDL
Current (V
DDL
=3.6V)
V
DDL
Current (V
DDL
= 2.625V)
0.3
7
5
30
10
8
Parameter
[1]
DC
Name
Description
Min.
40
Typ.
50
Max.
60
Unit
%
Duty Cycle is defined in Figure 1; t1/t2, 50% of
V
DD
t
3
Rising Edge Slew Rate Output Clock Rise Time, 20%
–
80% of
V
DD
/V
DDL
= 3.3V
Rising Edge Slew Rate Output Clock Rise Time, 20%
–
80% of
V
DDL
= 2.5V
Falling Edge Slew
Rate
V
DD
/V
DDL
= 3.3V
Falling Edge Slew
Rate
V
DDL
= 2.5V
Skew
Delay between related outputs at rising edge
Clock Jitter
Peak to Peak period jitter
PLL Lock Time
0.8
1.4
V/ns
t
3
0.6
1.2
V/ns
t
4
Output Clock Fall Time, 80%
–
20% of
0.8
1.4
V/ns
t
4
Output Clock Fall Time, 80%
–
20% of
0.6
1.2
V/ns
t5
t9
t10
200
250
3
ps
ps
ms
Note:
2.
Not 100% tested.
Figure 1. Duty Cycle Definition; DC = t2/t1.
Figure 2. Rise and Fall Time Definitions.
t1
t2
CLK
50%
50%
t3
CLK
80%
20%
t4
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