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參數(shù)資料
| 型號(hào)： | CY26049-5 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 51K |
| 代理商： | CY26049-5 |
ADVANCE
INFORMATION
CY26049-1
Document #: 38-07488 Rev. *A
Page 4 of 6
t
fs_lock
Failsafe Lock Time
Time for PLL to lock to ICLK (outputs phase aligned with
ICLK and Safe = High)
Actual mean frequency error vs. target
Output Clock Edge Rate, Measured from 20% to 80% of
V
DD
, C
LOAD
= 15pF. See
Figure 2
.
Output Clock Edge Rate, Measured from 20% to 80% of
V
DD
, C
LOAD
= 15pF. See
Figure 2
.
–
–
7
s
f
error
ER
Frequency Synthesis Error
Rising Edge Rate
–
0
–
2
ppm
V/ns
0.8
1.4
EF
Falling Edge Rate
0.8
1.4
2
V/ns
Voltage and Timing Definitions
Test Circuit
Ordering Information
Ordering Code
Package Type
Operating Temperature Range
Commercial 0 to 70°C
Commercial 0 to 70°C
CY26049ZC-1
CY26049ZC-1T
16-lead TSSOP
16-lead TSSOP—Tape and Reel
AC Electrical Specifications
(Commercial Temp: 0
°
to 70
°
C) (continued)
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
t1
t2
50%
50%
CLK
Figure 1. Duty Cycle Definition; DC = t2/t1
Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4
CLK
t3
t4
80%
20%
0.1uF
VDD
ICLK
0.1uF
VDD
CLKA
C
LOAD
C
LOAD
CLKB
16
4
3
2
1
9
10
11
12
13
15
14
5
6
7
8
18.432 MHz
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