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參數(shù)資料
| 型號： | CY26049-1 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大小： | 51K |
| 代理商： | CY26049-1 |
ADVANCE
INFORMATION
CY26049-1
Document #: 38-07488 Rev. *A
Page 3 of 6
Absolute Maximum Conditions
Supply Voltage (V
DD
)........................................–0.5 to +7.0V
DC Input Voltage........................................–0.5V to V
DD
+0.5
Storage Temperature (Non-condensing).....–55
°
C to +125
°
C
Junction Temperature ................................ –40
°
C to +125
°
C
Recommended Pullable Crystal Specifications
[1]
Data Retention @ Tj=125
°
C..................................> 10 years
Package Power Dissipation......................................350 mW
ESD (Human Body Model) MIL-STD-883....................2000V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Parameter
F
NOM
Description
Comments
Min.
–
Typ.
18.432
Max.
–
Unit
MHz
Nominal crystal frequency
Parallel resonance, fundamental
mode, AT cut
C
LNOM
R
1
R
3
/R
1
Nominal load capacitance
Equivalent series resistance (ESR)
Ratio of third overtone mode ESR to
fundamental mode ESR
Crystal drive level
Third overtone separation from 3*F
NOM
High side
Third overtone separation from 3*F
NOM
Low side
Crystal shunt capacitance
Ratio of shunt to motional capacitance
Crystal motional capacitance
Recommended Operating Conditions
–
–
3
14
–
–
–
25
–
pF
Fundamental mode
Ratio used because typical R
1
values
are much less than the maximum spec
No external series resistor assumed
DL
F
3SEPHI
F
3SEPLO
C
0
C
0
/C
1
C
1
–
0.5
–
–
–
–
18
2
–
mW
ppm
ppm
pF
400
–
–
180
14.4
–200
7
250
21.6
fF
Parameter
Description
Min.
3.15
0
–
0.05
Typ.
3.3
–
–
–
Max.
3.45
70
15
500
Unit
V
° C
pF
ms
V
DD
T
AC
C
LOAD
t
pu
Operating Voltage
Ambient Temperature (Commercial Temperature)
Max Output Load Capacitance
Power-up time for all V
DD
s to reach minimum specified
voltage (power ramps must be monotonic)
DC Electrical Specifications
(Commercial Temp: 0° to 70°C)
Parameter
I
OH
I
OL
V
IH
V
IL
I
IH
I
IL
C
IN
I
DD
Description
Test Conditions
Min.
12
12
0.7
–
–
–
–
–
Typ.
24
24
–
–
5
5
–
–
Max.
–
–
–
0.3
10
10
7
30
Unit
mA
mA
V
DD
V
DD
μ
A
μ
A
pF
mA
Output High Current
Output Low Current
Input High Voltage
Input High Voltage
Input High Current
Input Low Current
Input Capacitance
Supply Current
V
OH
= V
DD
– 0.5, V
DD
= 3.3V (source)
V
OL
= 0.5, V
DD
= 3.3V (sink)
CMOS Levels
CMOS Levels
V
IH
= V
DD
V
IL
= 0V
C
LOAD
= 15 pF, V
DD
= 3.45V
AC Electrical Specifications
(Commercial Temp: 0
°
to 70
°
C)
Parameter
f
ICLK-E
LR
DC = t
2
/t
1
T
PJIT1
Description
Test Conditions
Min.
–
–250
45
–
–
–
Typ.
8.00
–
50
–
–
–
Max.
–
+250
55
250
50
3
Unit
kHz
ppm
%
ps
ps
ms
Frequency, Input Clock
FailSafe
Lock Range
[2]
Output Duty Cycle
Clock Jitter; output > 5 MHz Period Jitter, Peak to Peak, 10,000 periods
RMS Period Jitter, RMS
PLL Lock Time
Time for PLL to lock within ± 150 ppm of target frequency
Input Clock Frequency, External Mode
Range of reference ICLK for Safe = High
Duty Cycle defined in
Figure 1
, measured at 50% of V
DD
t
6
Notes:
1.
2.
Ecliptek ECX-5761-18.432M meets these specifications.
Dependent on crystals chosen and crystal specs.
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