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參數(shù)資料
| 型號(hào)： | CY25812 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Spread Spectrum Clock Generator(擴(kuò)頻時(shí)鐘發(fā)生器) |
| 中文描述： | 擴(kuò)頻時(shí)鐘發(fā)生器（擴(kuò)頻時(shí)鐘發(fā)生器） |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 346K |
| 代理商： | CY25812 |
CY25811/12/14
Document Number: 38-07112 Rev. *F
Page 3 of 12
Spread% Selection
The CY25811/12/14 SSCG products provide Center-Spread, Down-Spread and No-Spread functions. The amount of Spread% is
selected by using 3-Level. S0 and S1 digital inputs and Spread% values are given in
Table 3
.
Table 3. Spread% Selection
3-Level Digital Inputs
S0, S1, and FRSEL digital inputs are designed to sense 3
different logic levels designated as High “1”, Low “0” and Middle
“M”. With this 3-Level digital input logic, the 3-Level Logic is able
to detect 9 different logic states.
S0, S1 and FRSEL pins include an on chip 20K (10K/10K)
resistor divider. No external application resistors are needed to
implement the 3-Level logic levels as shown below:
Logic Level “0”: 3–Level logic pin connected to GND.
Logic Level “M”: 3–Level logic pin left floating (no connection).
Logic Level “1”: 3–Level logic pin connected to V
DD
.
illustrates how to implement 3–Level Logic.Figure 2. 3–Level Logic
Modulation Rate
Spread Spectrum Clock Generators utilize frequency modulation
(FM) to distribute energy over a specific band of frequencies. The
maximum frequency of the clock (fmax), and minimum frequency
of the clock (fmin) determine this band of frequencies. The time
required to transition from fmin to fmax and back to fmin is the
period of the Modulation Rate. The Modulation Rate of SSCG
clocks are generally referred to in terms of frequency, or:
fmod = 1/Tmod.
The input clock frequency, fin, and the internal divider determine
the Modulation Rate.
In the case of CY25811/2/4 devices, the (Spread Spectrum)
modulation Rate, fmod, is given by the following formula:
fmod = fin/DR
where: fmod is the Modulation Rate; fin is the Input Frequency;
and DR is the Divider Ratio as given in
Table 4
. Notice that Input
Frequency Range is set by FRSEL.
Table 4. Modulation Rate Divider Ratios
XIN
(MHz)
FRSEL
S1 = 0
S0 = 0
Center
(%)
±1.4
±1.3
±1.2
±1.1
±1.4
±1.3
±1.2
±1.1
±1.4
±1.3
±1.2
±1.1
S1 = 0
S0 = M
Center
(%)
± 1.2
± 1.1
± 0.9
± 0.9
±1.2
±1.1
± 0.9
± 0.9
±1.2
±1.1
± 0.9
± 0.9
S1 = 0
S0 = 1
Center
(%)
± 0.6
± 0.5
± 0.5
± 0.4
± 0.6
± 0.5
± 0.5
± 0.4
± 0.6
± 0.5
± 0.5
± 0.4
S1 = M
S0 = 0
Center
(%)
± 0.5
± 0.4
± 0.4
± 0.3
± 0.5
± 0.4
± 0.4
± 0.3
± 0.5
± 0.4
± 0.4
± 0.3
S1 = 1
S0 = 1
Down
(%)
–3.0
–2.7
–2.5
–2.3
–3.0
–2.7
–2.5
–2.3
–3.0
–2.7
–2.5
–2.3
S1 = 1
S0 = 0
Down
(%)
–2.2
–1.9
–1.8
–1.7
–2.2
–1.9
–1.8
–1.7
–2.2
–1.9
–1.8
–1.7
S1 = M
S0 = 1
Down
(%)
–1.9
–1.7
–1.5
–1.4
–1.9
–1.7
–1.5
–1.4
–1.9
–1.7
–1.5
–1.4
S1 = 1
S0 = M
Down
(%)
–0.7
–0.6
–0.6
–0.5
–0.7
–0.6
–0.6
–0.5
–0.7
–0.6
–0.6
–0.5
S1 = M
S0 = M
No Spread
4-5
5-6
6-7
7-8
8-10
10-12
12-14
14-16
16-20
20-24
24-28
28-32
0
0
0
0
1
1
1
1
M
M
M
M
0
0
0
0
0
0
0
0
0
0
0
0
LOGIC
MIDDLE (M)
LOGIC
HIGH (H)
S0, S1
and
FRSEL
to VDD
S0, S1
and
FRSEL
UNCONNECTED
S0, S1
and
FRSEL
to VSS
VSS
LOGIC
LOW (0)
FRSEL
Input Frequency Range
(MHz)
4 to 8
8 to 16
16 to 32
Divider Ratio
(DR)
128
256
512
0
1
M
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CY25812SC | 制造商:Cypress Semiconductor 功能描述:PLL Frequency Synthesizer Single 8-Pin SOIC |
| CY25812SCT | 制造商:Cypress Semiconductor 功能描述:PLL Frequency Synthesizer Single 8-Pin SOIC T/R |
| CY25812SI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Spread Spectrum Clock Generator |
| CY25812SIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Spread Spectrum Clock Generator |
| CY25812SXC | 功能描述:鎖相環(huán) - PLL Reduction SSCGs COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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