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參數(shù)資料
| 型號： | CY25702XZZZ |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Programmable High-Frequency Crystal Oscillator (XO) |
| 中文描述： | 可編程高頻晶體振蕩器（XO） |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 124K |
| 代理商： | CY25702XZZZ |
CY25702
Document #: 38-07721 Rev. **
Page 3 of 7
Application Circuit
V
OH2
V
OL2
V
IH1
V
IL1
V
IH2
V
IL2
I
IH
I
IL
I
OZ
C
IN
I
VDD1
High Output Voltage
Low Output Voltage
Input High Voltage (pin 1)
Input Low Voltage (pin 1)
Input High Voltage (pin 1)
Input Low Voltage (pin 1)
Input High Current (pin 1)
Input Low Current (pin 1)
Output Leakage Current (pin 3) Three-state output, OE = 0
Input Capacitance (pin 1)
Supply Current
V
DD
= 3.3V , I
OH
= –8mA
V
DD
= 3.3V , I
OL
= 8mA
V
DD
= 5.0V
V
DD
= 5.0V
V
DD
= 3.3V
V
DD
= 3.3V
V
in
= V
DD
V
in
= V
SS
V
DD
-0.4
–
2.0
–
0.7V
DD
–
–
–
–10
–
–
–
–
–
–
–
–
–
–
–
5
–
–
V
V
V
V
V
V
μ
A
μ
A
μ
A
pF
mA
0.4
–
0.8
–
0.2V
DD
10
10
10
7
28
Pin 1, OE or PD#
V
DD
= 3.3V, CLK = 1 to 90 MHz,
C
LOAD
= 0, OE = V
DD
V
DD
= 3.3V, CLK = 1 to 90 MHz,
C
LOAD
= 0, OE = GND
V
DD
= 5.0V, CLK = 1 to 125 MHz,
C
LOAD
= 0, OE = V
DD
V
DD
= 5.0V, CLK = 1 to 125 MHz,
C
LOAD
= 0, OE = GND
PD# = GND
–20 to +70°C
Ta = 25°C, First Year
Three drops on a hard board from 750 mm or
excitation test with 29.400m/s
2
x 0.3ms x 1/2
sinewave in three directions
I
VDD2
Supply Current
–
–
16
mA
I
VDD3
Supply Current
–
–
45
mA
I
VDD4
Supply Current
–
–
30
mA
I
PD#
FS
AG
SR
Power Down Current
Frequency Stability
Aging
Shock Resistance
–
–
–
–
–
50
50
5
20
μ
A
ppm
ppm
ppm
–50
–5
–20
AC Electrical Characteristics
Parameter
DC
t
R
t
F
T
OE1
Description
Condition
Min.
40
–
–
–
Typ.
50
–
–
150
Max.
60
4.0
4.0
350
Unit
%
ns
ns
ns
Output Duty Cycle
Output Rise Time
Output Fall Time
Output Disable Time (pin1 = OE) Time from falling edge on OE to stopped
outputs (Asynchronous)
Output Enable Time (pin1 = OE) Time from rising edge on OE to outputs at a
valid frequency (Asynchronous)
PLL Lock Time
Time for CLK to reach valid frequency
Start-up time out of Power Down PD# pin Low to High
Power Down Delay Time
PD# pin Low to CLK Low (Asynchronous)
CLK, Measured at V
DD
/2
20%–80% of V
DD,
C
L
= 15 pF
20%–80% of V
DD,
C
L
= 15 pF
T
OE2
–
150
350
ns
T
LOCK
T
SU
T
PDD
–
–
–
–
–
–
10
5
25
ms
ms
ns
DC Electrical Characteristics
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
0.1uF
VDD
1
2
3
4
OE/PD#
VSS
CLK
VDD
Power
CY25702
(GND if PD#)
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