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參數(shù)資料
| 型號(hào)： | CY25566 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Spread Spectrum Clock Generator |
| 中文描述： | 擴(kuò)頻時(shí)鐘發(fā)生器 |
| 文件頁(yè)數(shù)： | 7/9頁(yè) |
| 文件大?。?/td> | 116K |
| 代理商： | CY25566 |
CY25566
Document #: 38-07429 Rev. *A
Page 7 of 9
Absolute Maximum Ratings
[1, 2]
Supply Voltage (V
DD
: .......................................................+6V
Operating Temperature:......................................0
°
C to 70
°
C
Storage Temperature ..................................
–
65
°
C to +150
°
C
Table 4. DC Electrical Characteristics
V
DD
= 3.3V, Temp. = 25
°
C, unless otherwise noted
Parameter
Description
V
DD
Power Supply Range
±10%
V
INH
Input High Voltage
S0 and S1 only.
V
INM
Input Middle Voltage
S0 and S1 only.
V
INL
Input Low Voltage
S0 and S1 only.
V
OH1
Output High Voltage
I
OH
= 6 ma, SSCLKa
V
OH2
Output High Voltage
I
OH
= 20 ma, SSCLKb
V
OL1
Output Low Voltage
I
OH
= 6 ma, SSCLKa
V
OL2
Output Low Voltage
I
OH
= 20 ma, SSCLKb
C
in1
Input Capacitance
Xin/CLK (Pin 1)
C
in2
Input Capacitance
Xout (Pin 8)
C
in2
Input Capacitance
All input pins except 1.
I
DD1
Power Supply Current
FIN = 40 MHz,15 pF@all outputs
I
DD1
Power Supply Current
FIN = 40 MHz, No Load
I
DD2
Power Supply Current
FIN = 165 MHz,15 pF@all outputs
I
DD2
Power Supply Current
FIN = 165 MHz, No Load
Conditions
Min.
2.97
0.85V
DD
0.40V
DD
0.0
2.4
2.0
Typ.
3.3
V
DD
0.50V
DD
0.0
Max.
3.63
V
DD
0.60V
DD
0.15V
DD
Unit
V
V
V
V
V
V
V
V
pF
pF
pF
mA
mA
mA
mA
0.4
1.2
5
10
5
32
28
80
60
3
6
3
4
8
4
27
21
68
48
Table 5. Electrical Timing Characteristics
V
DD
= 3.3V, T = 25
°
C and C
L
= 15 pF, unless otherwise noted. Rise/Fall @ 0.4
–
2.4V,
Duty@1.5V
Parameter
I
CLKFR
t
RISE(a)
t
FALL(a)
t
RISE(a+b)
t
FALL(a+b)
t
RISE(a+b)
t
FALL(a+b)
t
RISE(REF)
t
FALL(REF)
D
TYin
D
TYout
C
CJ1
C
CJ2
REFOUT
Description
Conditions
Min.
25
1.0
1.0
1.2
1.2
1.1
1.1
1.0
1.0
30
45
Typ.
Max
200
1.6
1.6
1.8
1.8
1.7
1.7
1.6
1.6
70
55
400
600
108
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
%
%
ps
ps
MHz
Input Clock Frequency Range Non-crystal, 3.0V Pk
–
Pk ext. source
Clock Rise Time
SSCLK1a or SSCLK1b, Freq = 100 MHz
Clock Fall Time
SSCLK1a or SSCLK1b, Freq = 100 MHz
Clock Rise Time
SSCLK1(a+b), CL = 33 pF, 100 MHz
Clock Fall Time
SSCLK1(a+b), CL = 33 pF, 100 MHz
Clock Rise Time
SSCLK1(a+b), CL = 33 pF, 200 MHz
Clock Fall Time
SSCLK1(a+b), CL = 33 pF, 200 MHz
Clock Rise Time
REFOUT, Pin 3, CL = 15 pF, 50 MHz
Clock Fall Time
REFOUT, Pin 3, CL = 15 pF, 50 MHz
Input Clock Duty Cycle
XIN/CLK (Pin)
Output Clock Duty Cycle
SSCLK1a/b (Pin 8 and 9)
Cycle-to-Cycle Jitter
F = 100 MHz, SSCLK1a/b CL = 33 pF
Cycle-to-Cycle Jitter
F = 200 MHz, SSCLK1a/b CL = 33 pF
Refout Frequency Range
CL = 15 pF
1.3
1.3
1.5
1.5
1.4
1.4
1.3
1.3
50
50
300
500
25
Note:
1.
2.
Operation at any Absolute Maximum Rating is not implied.
Single Power Supply:
The voltage on any input or I/O pin cannot exceed the power pin during power-up.
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